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    From Edward Rawde@21:1/5 to All on Sat May 24 16:31:05 2025
    Is anyone using QSpice yet and if so can they tell me why a simulation of this simple jfet astable looks different in QSpice?

    In LTSpice the simulated cycles (when it starts after about 40 seconds) look fine at the drain of each FET and repeat almost
    exactly.

    With exactly the same circuit in QSpice there seems to be some kind of simulation granularity issue.
    Maybe there's a simulation parameter I need to adjust.

    I'll try posting the QSpice schematic if anyone is interested but not sure how successful that will be.

    QSpice includes the UF3C170400K3S which may be of use to those people wanting to simulate similar things.

    Version 4.1
    SHEET 1 1396 772
    WIRE -16 -512 -240 -512
    WIRE 496 -512 -16 -512
    WIRE -16 -432 -16 -512
    WIRE 496 -432 496 -512
    WIRE -16 -272 -16 -352
    WIRE 32 -272 -16 -272
    WIRE 64 -272 32 -272
    WIRE 176 -272 128 -272
    WIRE 352 -272 304 -272
    WIRE 496 -272 496 -352
    WIRE 496 -272 416 -272
    WIRE -240 -256 -240 -512
    WIRE -16 -192 -16 -272
    WIRE 496 -192 496 -272
    WIRE 176 -128 304 -272
    WIRE 176 -128 32 -128
    WIRE 304 -128 176 -272
    WIRE 448 -128 304 -128
    WIRE 176 16 176 -128
    WIRE 304 16 304 -128
    WIRE -16 32 -16 -96
    WIRE 496 32 496 -96
    WIRE -240 208 -240 -176
    WIRE -16 208 -16 112
    WIRE -16 208 -240 208
    WIRE 176 208 176 96
    WIRE 176 208 -16 208
    WIRE 304 208 304 96
    WIRE 304 208 176 208
    WIRE 496 208 496 112
    WIRE 496 208 304 208
    WIRE -240 240 -240 208
    FLAG -240 240 0
    FLAG 32 -272 D1
    SYMBOL njf 448 -192 R0
    WINDOW 0 0 -11 Left 2
    WINDOW 3 -59 98 Left 2
    SYMATTR InstName J1
    SYMATTR Value 2N3819
    SYMBOL njf 32 -192 M0
    WINDOW 0 7 -9 Left 2
    WINDOW 3 -64 100 Left 2
    SYMATTR InstName J2
    SYMATTR Value 2N3819
    SYMBOL res -32 -448 R0
    SYMATTR InstName R1
    SYMATTR Value 3.3k
    SYMBOL res 480 -448 R0
    SYMATTR InstName R2
    SYMATTR Value 3.3k
    SYMBOL voltage -240 -272 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL res 480 16 R0
    SYMATTR InstName R7
    SYMATTR Value 1k
    SYMBOL res -32 16 R0
    SYMATTR InstName R3
    SYMATTR Value 1k
    SYMBOL res 160 0 R0
    SYMATTR InstName R4
    SYMATTR Value 10Meg
    SYMBOL res 288 0 R0
    SYMATTR InstName R5
    SYMATTR Value 10Meg
    SYMBOL cap 128 -288 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 100n
    SYMBOL cap 416 -288 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C4
    SYMATTR Value 100n
    TEXT -200 240 Left 2 !.tran 100

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Edward Rawde on Sat May 24 20:28:36 2025
    "Edward Rawde" <[email protected]d> wrote in message news:100taaa$v6s$[email protected]...
    Is anyone using QSpice yet and if so can they tell me why a simulation of this simple jfet astable looks different in QSpice?


    A bit more research finds that the answer to my own question seems to be to set the maximum step size which I did with
    .options MAXSTEP=1ms

    But there are still some strange artifacts on most of the horizontal tops of the drain waveforms.

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    * Origin: fsxNet Usenet Gateway (21:1/5)