https://www.dropbox.com/scl/fi/inzf0ykioxuh061w16vgj/P978_PCB_Apr_23.jpg?rlkey=qkyki2uzcg0xsczpjh11e2ypc&raw=1
This is an 8-channel isolated electronic dummy load that can be
programmed to look like a resistor in series with an inductor. To
simulate solenoids or motor windings or whatever.
It's a 6-layer board. Now we need to run 64 controlled-impedance
traces from the FPGA out into the channels. They will be asymmetric
striplines, between plane layers 2 and 4.
The catch seems to be that the GPIOs on this FPGA (Efinix T20) are not
all the same, and it's not obvious if the FPGA outputs can reasonably
act like source terminations.
I'm talking to some SPI ADCs at 24 MHz, which gives me a 41 ns timing
window. And I'm losing time in isolators both ways.
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