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  • MOSFET Analog Switch Question

    From Christopher Howard@21:1/5 to All on Sat Apr 19 12:48:23 2025
    Hi, I have some DG212BDJ Quad SPST CMOS Analog Switches. I am wondering
    if there is some significance, for each switch, to how the source and
    drain pins are used/fed. The data sheet says Analog Signal Range
    (V_Analog) is +/- 15 V, so it doesn't matter which way the current is
    moving across source and drain pins, right?


    Christopher Howard

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  • From Edward Rawde@21:1/5 to Christopher Howard on Sat Apr 19 17:34:23 2025
    "Christopher Howard" <[email protected]> wrote in message news:[email protected]...
    Hi, I have some DG212BDJ Quad SPST CMOS Analog Switches. I am wondering
    if there is some significance, for each switch, to how the source and
    drain pins are used/fed. The data sheet says Analog Signal Range
    (V_Analog) is +/- 15 V, so it doesn't matter which way the current is
    moving across source and drain pins, right?

    The data sheet I'm looking at (Revision 01 Jan 2025) has this on the first page:
    "All devices feature true bi-directional performance in the on
    condition, and will block signals to the supply levels in the off
    condition."
    I've not so far read the data sheet in any level of detail.
    Keep your analog signals within v- to v+



    Christopher Howard

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  • From Bill Sloman@21:1/5 to All on Sun Apr 20 15:06:14 2025
    On 20/04/2025 7:41 am, JM wrote:
    On Sat, 19 Apr 2025 12:48:23 -0800, Christopher Howard <[email protected]> wrote:

    Hi, I have some DG212BDJ Quad SPST CMOS Analog Switches. I am wondering
    if there is some significance, for each switch, to how the source and
    drain pins are used/fed. The data sheet says Analog Signal Range
    (V_Analog) is +/- 15 V, so it doesn't matter which way the current is
    moving across source and drain pins, right?

    Right. The switch will be made with parallel PMOS/NMOS.

    The data sheetx doesn't say that explicitly - they mostly just says that
    it is a CMOS part - but it is clearly implied.

    https://www.analog.com/media/en/technical-documentation/data-sheets/dg202-dg212.pdf

    https://www.vishay.com/docs/61556/dg211.pdf

    There should be application notes around that go into more detail, but
    Google doesn't seem to want to find them for me.

    --
    Bill Sloman, Sydney

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  • From john larkin@21:1/5 to [email protected] on Sat Apr 19 21:46:48 2025
    On Sat, 19 Apr 2025 12:48:23 -0800, Christopher Howard <[email protected]> wrote:

    Hi, I have some DG212BDJ Quad SPST CMOS Analog Switches. I am wondering
    if there is some significance, for each switch, to how the source and
    drain pins are used/fed. The data sheet says Analog Signal Range
    (V_Analog) is +/- 15 V, so it doesn't matter which way the current is
    moving across source and drain pins, right?


    Christopher Howard

    It should be symmetric, happy conducting in either direction.

    Don't let the signals go beyond the rails.

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  • From Bill Sloman@21:1/5 to john larkin on Sun Apr 20 21:51:27 2025
    On 20/04/2025 2:46 pm, john larkin wrote:
    On Sat, 19 Apr 2025 12:48:23 -0800, Christopher Howard <[email protected]> wrote:

    Hi, I have some DG212BDJ Quad SPST CMOS Analog Switches. I am wondering
    if there is some significance, for each switch, to how the source and
    drain pins are used/fed. The data sheet says Analog Signal Range
    (V_Analog) is +/- 15 V, so it doesn't matter which way the current is
    moving across source and drain pins, right?

    It should be symmetric, happy conducting in either direction.

    Only in the sense of conducting both ways. N-MOSFets tend to be more
    conductive than P-MOSFets. If they make the P-MOSFets bigger than the
    N-MOSFets they can can balance the channel resistances, but not the
    channel capacitances.

    Don't let the signals go beyond the rails.

    That would reverse bias the isolation diodes and feed current into the
    rails, and elsewhere if you are unlucky. The effects can be unfortunate.

    --
    Bill Sloman, Sydney

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  • From Edward Rawde@21:1/5 to Bill Sloman on Sun Apr 20 13:29:17 2025
    "Bill Sloman" <[email protected]> wrote in message news:vu1vc7$3232m$[email protected]...
    On 20/04/2025 7:41 am, JM wrote:
    On Sat, 19 Apr 2025 12:48:23 -0800, Christopher Howard
    <[email protected]> wrote:

    Hi, I have some DG212BDJ Quad SPST CMOS Analog Switches. I am wondering
    if there is some significance, for each switch, to how the source and
    drain pins are used/fed. The data sheet says Analog Signal Range
    (V_Analog) is +/- 15 V, so it doesn't matter which way the current is
    moving across source and drain pins, right?

    Right. The switch will be made with parallel PMOS/NMOS.

    The data sheetx doesn't say that explicitly - they mostly just says that it is a CMOS part - but it is clearly implied.

    https://www.analog.com/media/en/technical-documentation/data-sheets/dg202-dg212.pdf

    https://www.vishay.com/docs/61556/dg211.pdf

    There should be application notes around that go into more detail, but Google doesn't seem to want to find them for me.

    This might be useful: https://www.google.com/search?q=analog+switch+application+note

    And this:
    https://www.google.com/search?q=AN208+analog+switch


    --
    Bill Sloman, Sydney

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  • From legg@21:1/5 to [email protected] on Mon Apr 21 01:48:43 2025
    On Sat, 19 Apr 2025 12:48:23 -0800, Christopher Howard <[email protected]> wrote:

    Hi, I have some DG212BDJ Quad SPST CMOS Analog Switches. I am wondering
    if there is some significance, for each switch, to how the source and
    drain pins are used/fed. The data sheet says Analog Signal Range
    (V_Analog) is +/- 15 V, so it doesn't matter which way the current is
    moving across source and drain pins, right?


    Christopher Howard

    Linearity is probably only a condition when looking at
    ~5V single supply analog switches.

    RL

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  • From Phil Hobbs@21:1/5 to john larkin on Mon Apr 21 11:38:01 2025
    On 2025-04-20 00:46, john larkin wrote:
    On Sat, 19 Apr 2025 12:48:23 -0800, Christopher Howard <[email protected]> wrote:

    Hi, I have some DG212BDJ Quad SPST CMOS Analog Switches. I am wondering
    if there is some significance, for each switch, to how the source and
    drain pins are used/fed. The data sheet says Analog Signal Range
    (V_Analog) is +/- 15 V, so it doesn't matter which way the current is
    moving across source and drain pins, right?


    Christopher Howard

    It should be symmetric, happy conducting in either direction.

    Don't let the signals go beyond the rails.

    Yup. Otherwise, typically all the channels will get connected together
    by way of the substrate. It's a puzzle to debug, the first time it
    happens to you--it's always the channel you're not focusing on that's
    railed. ;)

    If you're worried about linearity, do note the switch resistance vs.
    signal voltage curves, which are usually sort of moustache-shaped.

    To avoid signal distortion, don't draw significant current through an
    analog switch.

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

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  • From john larkin@21:1/5 to pcdhSpamMeSenseless@electrooptical. on Mon Apr 21 11:33:47 2025
    On Mon, 21 Apr 2025 11:38:01 -0400, Phil Hobbs <[email protected]> wrote:

    On 2025-04-20 00:46, john larkin wrote:
    On Sat, 19 Apr 2025 12:48:23 -0800, Christopher Howard
    <[email protected]> wrote:

    Hi, I have some DG212BDJ Quad SPST CMOS Analog Switches. I am wondering
    if there is some significance, for each switch, to how the source and
    drain pins are used/fed. The data sheet says Analog Signal Range
    (V_Analog) is +/- 15 V, so it doesn't matter which way the current is
    moving across source and drain pins, right?


    Christopher Howard

    It should be symmetric, happy conducting in either direction.

    Don't let the signals go beyond the rails.

    Yup. Otherwise, typically all the channels will get connected together
    by way of the substrate. It's a puzzle to debug, the first time it
    happens to you--it's always the channel you're not focusing on that's
    railed. ;)

    Exactly. And the series fets will start to conduct before the ESD
    diodes clamp the swing.

    Roger the first-time perplexity.



    If you're worried about linearity, do note the switch resistance vs.
    signal voltage curves, which are usually sort of moustache-shaped.

    Don't load the switches if you want linearity.


    To avoid signal distortion, don't draw significant current through an
    analog switch.

    I just said that!

    Charge injection is fun too. Drives some opamps bonkers.



    Cheers

    Phil Hobbs

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