1. Forum
  2. Usenet
  3. SCI.ELECTRONICS.DESIGN

  • An LTSpice test bed for the gain control FET in "low distortion" oscill

    From Bill Sloman@21:1/5 to All on Sun Dec 22 01:39:21 2024
    The Jim Williams low distortion Wein bridge depends on a FET for
    amplitude control, but the FET isn't the perFectly linear resistor we'd
    like it to be.

    And minimising the rectifier ripple in the gain control voltage applied
    to the gate of the FET is tricky.The test bed example below is set to
    apply 10uV of 2kHz ripple, which is less than any of my circuits can
    manage - 2mV is closer to what the circuit I've posted could manage.

    I've put together a little LTSpice test bed to try to get some idea of
    how non-linear the FET channel is.

    Mind the line wraps - the last three lines should be a single line in
    the .asc file.

    It looks as if there about 70uV of higher harmonic content in the 10.4mV
    peak to peak voltage across the FET for the 1V peak to peak 1kHz test
    signal.

    Version 4
    SHEET 1 1252 680
    WIRE 304 -592 -496 -592
    WIRE 304 -512 304 -592
    WIRE 64 -496 -96 -496
    WIRE 64 -448 64 -496
    WIRE -96 -432 -96 -496
    WIRE 64 -336 64 -368
    WIRE 304 -336 304 -432
    WIRE 304 -336 64 -336
    WIRE -496 -304 -496 -592
    WIRE 64 -256 64 -336
    WIRE 304 -192 304 -336
    WIRE 64 -128 64 -176
    WIRE 112 -128 64 -128
    WIRE 256 -128 112 -128
    WIRE 64 -80 64 -128
    WIRE -496 48 -496 -224
    WIRE -128 48 -496 48
    WIRE -96 48 -96 -352
    WIRE -96 48 -128 48
    WIRE 304 48 304 -96
    WIRE 304 48 -96 48
    WIRE -128 80 -128 48
    WIRE -496 112 -496 48
    WIRE -496 240 -496 192
    WIRE 64 240 64 0
    WIRE 64 240 -496 240
    FLAG 112 -128 Fet-gate
    FLAG -128 80 0
    SYMBOL res 80 16 R180
    WINDOW 0 31 76 Left 2
    WINDOW 3 31 40 Left 2
    SYMATTR InstName R1
    SYMATTR Value 10k
    SYMATTR SpiceLine tol=0.1
    SYMBOL res 48 -272 R0
    WINDOW 0 43 37 Left 2
    WINDOW 3 47 73 Left 2
    SYMATTR InstName R2
    SYMATTR Value 10k
    SYMATTR SpiceLine tol=0.1
    SYMBOL njf 256 -192 R0
    SYMATTR InstName J1
    SYMATTR Value MMBF4391
    SYMBOL res 288 -528 R0
    WINDOW 0 43 37 Left 2
    WINDOW 3 47 73 Left 2
    SYMATTR InstName R3
    SYMATTR Value 5k
    SYMATTR SpiceLine tol=0.1
    SYMBOL voltage -496 -320 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V1
    SYMATTR Value SINE(0 1 1kHz 0 0 0 1000)
    SYMBOL voltage -496 96 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V2
    SYMATTR Value SINE(7.724 0.00001 2k 0 0 90 2000)
    SYMBOL voltage -96 -448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V3
    SYMATTR Value 7.724
    SYMBOL res 48 -464 R0
    WINDOW 0 43 37 Left 2
    WINDOW 3 47 73 Left 2
    SYMATTR InstName R4
    SYMATTR Value 20k
    SYMATTR SpiceLine tol=0.1
    TEXT 128 144 Left 2 !.tran 0 1s 0s startup
    TEXT -648 304 Left 2 !.MODEL MMBF4391 NJF VTO=-4.6
    BETA=0.02779LAMBDA=0.00595 RD=1 RS=1 IS=1e-14 CGD=14p CGS=10.5p PB=1 B=1KF=1e-18 AF=1 FC=0.5 mfg=Motorola

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Bill Sloman on Sun Dec 22 17:18:02 2024
    On 22/12/2024 1:39 am, Bill Sloman wrote:
    The Jim Williams low distortion Wein bridge depends on a FET for
    amplitude control, but the FET isn't the perFectly linear resistor we'd
    like it to be.

    And minimising the rectifier ripple in the gain control voltage applied
    to the gate of the FET is tricky.The test bed example below is set to
    apply 10uV of 2kHz ripple, which is less than any of my circuits can
    manage - 2mV is closer to what the circuit I've posted could manage.

    I've put together a little LTSpice test bed to try to get some idea of
    how non-linear the FET channel is.

    It looks as if there about 70uV of higher harmonic content in the 10.4mV
    peak to peak voltage across the FET for the 1V peak to peak 1kHz test
    signal.

    Tinkering got that down a bit to about 18uV with 3.5mV of 2kHz ripple -
    that seems to be the sweet spot where the 2kHz and 3kHz harmonics are
    both about 60dB below the 1kHz fundamental - moving away from that
    pushes one up and the other down.

    What's going on in the FET is still a mystery to me. I'd have to dig
    into the FET Spice model to get any idea. The semi-conductor physics
    should be well understood - I've got a textbook on my bookshelf that
    claims to spell it out - but translating that into a hand-on feel for
    what's actually going on isn't something I've ever needed to do.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)