Hey guys, I've been going over some of the timings for writing data from a peripheral card on to the Apple IIe bus and just when I think I have it, I get confused again. This is for an accelerator I'm working on that replaces the 6502, and it seems to be
working for all reads but some errors on the writes so I want to make sure I have it right. I'm using a IIgs for testing but want to make this work across the range of Apple IIs if possible.

In the DMA tech note for the IIe it says that the data bus is valid until Phase 0 falls, and even presents a write scenario where you can gate your write using the 7M signal and hold it *until* Phase 0 falls, but in Sather's IIe book pages 4-7 and 4-8 it
states a couple of times that write is held valid for some time *after* Phase 2 falls, and Phase 2 falls in worst-case 65ns after Phase 0 falls, which means I have to hold the write for some time after Phase 0 falls. I know I must be reading this wrong
so would someone enlighten me?

I'd like my peripheral-card read/write to work across the Apple II range so I'm wondering if anyone has any timing data on when it's safe to start fiddling with the Address and Data buses and R/W line and when they need to be held stable and valid.

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On 8/2/2022 11:31 AM, Anthony Ortiz wrote:

Hey guys, I've been going over some of the timings for writing data from a peripheral card on to the Apple IIe bus and just when I think I have it, I get confused again. This is for an accelerator I'm working on that replaces the 6502, and it seems to

be working for all reads but some errors on the writes so I want to make sure I have it right. I'm using a IIgs for testing but want to make this work across the range of Apple IIs if possible.

In the DMA tech note for the IIe it says that the data bus is valid until Phase 0 falls, and even presents a write scenario where you can gate your write using the 7M signal and hold it *until* Phase 0 falls, but in Sather's IIe book pages 4-7 and 4-8

it states a couple of times that write is held valid for some time *after* Phase 2 falls, and Phase 2 falls in worst-case 65ns after Phase 0 falls, which means I have to hold the write for some time after Phase 0 falls. I know I must be reading this
wrong so would someone enlighten me?

I'd like my peripheral-card read/write to work across the Apple II range so I'm wondering if anyone has any timing data on when it's safe to start fiddling with the Address and Data buses and R/W line and when they need to be held stable and valid.

I've struggled with Apple II timing myself so I feel your pain.
I know next to nothing about how accelerators work but...

Since you are using a IIgs for testing you should be aware that phase 2
on the 65816 in not the same as phase 2 on a 6502 (see Apple IIgs tech
note #68). I believe the phase 2 clock on the 6502 is the same as the
phase 0 clock on the Apple peripheral bus. The phase 2 clock on the
65816 actually varies its period.

You mentioned DMA so I'm thinking that's the timing you are going for.
The IIgs hardware reference says (in reference to cards that work on
other Apple II models) that they will *probably* work if they assert and
remove the /DMA signal within 200 nanoseconds of the rising edge of
phase 0. It also says that normally the IIgs should be running at 1.024
MHz when performing DMAs. There are exceptions to this if you are only accessing fast ram or rom.
Also with the IIgs you need to set the DMA bank register.

If you are using a logic device (FPGA, etc.), here is a link to Alex
Freed's verilog code for DMA timing on an Apple IIe which may help:

https://sourceforge.net/p/jatcb/code/HEAD/tree/dma.v

Lastly, I like to synchronize all the clocks on the card whether or not
I'm using the 7Mz Apple clock as the system clock or a clock on the card.

Charlie

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You mentioned DMA so I'm thinking that's the timing you are going for.
The IIgs hardware reference says (in reference to cards that work on
other Apple II models) that they will *probably* work if they assert and remove the /DMA signal within 200 nanoseconds of the rising edge of
phase 0. It also says that normally the IIgs should be running at 1.024
MHz when performing DMAs. There are exceptions to this if you are only accessing fast ram or rom.
Also with the IIgs you need to set the DMA bank register.

If you are using a logic device (FPGA, etc.), here is a link to Alex
Freed's verilog code for DMA timing on an Apple IIe which may help:

https://sourceforge.net/p/jatcb/code/HEAD/tree/dma.v

Lastly, I like to synchronize all the clocks on the card whether or not
I'm using the 7Mz Apple clock as the system clock or a clock on the card.

Charlie

Hey Charlie,

I'm new to VHDL so I was trying to trigger on both the rising/falling edges of 7M to create a counter that offsets from Phase0 rise/fall, that way I could use the counter as a point where to perform certain logic such as read and writes. However, I
quickly learned that I know nothing and that just because it's valid VHDL doesn't mean it's synthesizable, lol. I'm just going to create a 100mhz clock so that I have 10ns granularity and use that instead.

You mention the Carte Blanche; have you done a lot of prototyping with it? Do you have any projects you're working on?

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On 8/10/2022 1:19 PM, Anthony Ortiz wrote:

You mentioned DMA so I'm thinking that's the timing you are going for.
The IIgs hardware reference says (in reference to cards that work on
other Apple II models) that they will *probably* work if they assert and
remove the /DMA signal within 200 nanoseconds of the rising edge of
phase 0. It also says that normally the IIgs should be running at 1.024
MHz when performing DMAs. There are exceptions to this if you are only
accessing fast ram or rom.
Also with the IIgs you need to set the DMA bank register.

If you are using a logic device (FPGA, etc.), here is a link to Alex
Freed's verilog code for DMA timing on an Apple IIe which may help:

https://sourceforge.net/p/jatcb/code/HEAD/tree/dma.v

Lastly, I like to synchronize all the clocks on the card whether or not
I'm using the 7Mz Apple clock as the system clock or a clock on the card.

Charlie

Hey Charlie,

I'm new to VHDL so I was trying to trigger on both the rising/falling edges of 7M to create a counter that offsets from Phase0 rise/fall, that way I could use the counter as a point where to perform certain logic such as read and writes.

I program in verilog and I was completely new to it when I started with
the Carte Blanche card.
I'm still pretty much a novice.

However, I quickly learned that I know nothing and that just because
it's valid VHDL doesn't mean it's synthesizable, lol. I'm just going to
create a 100mhz clock so that I have 10ns granularity and use that instead.

I found that out too. ;-)

It is my understanding that triggering on both the rising and falling
edge of a clock signal won't work because the flip-flops in the chip
don't support double clocking. At least they don't on the FPGAs on the
Carte Blanche and Carte Blanche II card.

You mention the Carte Blanche; have you done a lot of prototyping with it?

Most of what I've done is with video. I originally modified Alex
Freed's JAT code for the Carte Blanche so that I could have the colored
text, background and borders on a //e (like a IIgs has).
My next project was to make a video only card for the IIgs with the SHR
video modes.
After that I made a video card for the //e that displays SHR graphics.
I also added code to allow loading a bitstream to the flash memory on
the Carte Blanche from the Apple //e.

When the Carte Blanche II came out I moved my projects to it.
Also added HDMI output and 800x600 resolution so that the IIgs side
borders are visible.

Do you have any projects you're working on?

One project that I started quite a while ago is using the onboard micro
SD card as a hard drive (something like the CFFA3000 does with USB)
while still maintaining the VGA/HDMI video.
Unfortunately, life gets in the way and I haven't done much with it lately.

Here's my website for more information:

http://noboot.com/charlie/Charlie's%20Stuff.htm

Charlie

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