1. Forum
  2. Usenet
  3. COMP.SYS.APPLE2

  • Apple II TTL to 3.3 logic

    From Anthony Ortiz@21:1/5 to All on Mon Jul 18 22:29:50 2022
    I'm redesigning some circuitry I have on my peripheral board to a modern 3.3v CPLD and read some articles on the interwebs stating that TTL logic is about 3.4 volts so I might get away with interfacing a 3.3 chip straight from the Apple IIe bus and do
    away with the 245 transceivers I'm using. My gut feeling is to have the 245's there just in case and err on the safe side, but I'm curious as to what you guys think about going raw from the Apple II bus to a 3.3v GPIO that's not that tolerant.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Anthony Ortiz@21:1/5 to Michael J. Mahon on Tue Jul 19 19:10:38 2022
    On Tuesday, July 19, 2022 at 10:05:57 PM UTC-4, Michael J. Mahon wrote:
    I'm redesigning some circuitry I have on my peripheral board to a modern 3.3v CPLD and read some articles on the interwebs stating that TTL logic is about 3.4 volts so I might get away with interfacing a 3.3 chip straight from the Apple IIe bus and do away with the 245 transceivers I'm using. My gut feeling is to have the 245's there just in case and err on the safe side, but I'm curious as to what you guys think about going raw from the Apple II bus to a 3.3v GPIO that's not that tolerant.

    Nope—you’ll need level-changing circuitry and keep the 245’s. The Apple II
    bus is *definitly* a TTL bus.

    --
    -michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com

    Thanks Michael, you're always a great help and an invaluable source of all things Apple II. :)

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Michael J. Mahon@21:1/5 to Anthony Ortiz on Tue Jul 19 21:05:50 2022
    Anthony Ortiz <[email protected]> wrote:
    I'm redesigning some circuitry I have on my peripheral board to a modern
    3.3v CPLD and read some articles on the interwebs stating that TTL logic
    is about 3.4 volts so I might get away with interfacing a 3.3 chip
    straight from the Apple IIe bus and do away with the 245 transceivers I'm using. My gut feeling is to have the 245's there just in case and err on
    the safe side, but I'm curious as to what you guys think about going raw
    from the Apple II bus to a 3.3v GPIO that's not that tolerant.


    Nope—you’ll need level-changing circuitry and keep the 245’s. The Apple II
    bus is *definitly* a TTL bus.

    --
    -michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From David Schmidt@21:1/5 to Anthony Ortiz on Wed Jul 20 02:04:41 2022
    On 7/19/22 10:10 PM, Anthony Ortiz wrote:
    On Tuesday, July 19, 2022 at 10:05:57 PM UTC-4, Michael J. Mahon wrote:
    I'm redesigning some circuitry I have on my peripheral board to a modern >>> 3.3v CPLD and read some articles on the interwebs stating that TTL logic >>> is about 3.4 volts so I might get away with interfacing a 3.3 chip
    straight from the Apple IIe bus and do away with the 245 transceivers I'm >>> using. My gut feeling is to have the 245's there just in case and err on >>> the safe side, but I'm curious as to what you guys think about going raw >>> from the Apple II bus to a 3.3v GPIO that's not that tolerant.

    Nope—you’ll need level-changing circuitry and keep the 245’s. The Apple II
    bus is *definitly* a TTL bus.

    --
    -michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com

    Thanks Michael, you're always a great help and an invaluable source of all things Apple II. :)

    I have to agree. What an absolute treasure you are, Michael. Thank you.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)