https://lore.kernel.org/all/[email protected]/T/
Necasek acts as deep safety....
" OK, here's the goods I promised. The NCR 86C01 is an MCA interface
chip that handles enabling/diabling IRQ, dma interfacing, IO port
selection and other fun stuff. It takes up 16 addresses, and the chip
it is connnected to gets the following 16. Registers are as follows:
Offsets 0-1 : Card ID
Offset 2 : Mode enable register --
Bit 7 : Data Word width (1 = 16, 0 = 8)
Bit 6 : IRQ enable (1 = enabled)
Bits 5,4 : IRQ select
0 0 : IRQ 3
0 1 : IRQ 5
1 0 : IRQ 7
1 1 : IRQ 9
Bits 3-1 : Base Address
0 0 0 : <disabled>
0 0 1 : 0x0240
0 1 0 : 0x0340
0 1 1 : 0x0400
1 0 0 : 0x0420
1 0 1 : 0x3240
1 1 0 : 0x8240
1 1 1 : 0xA240
Bit 0 : Card enable (1 = enabled)
Offset 3 : DMA control register --
Bit 7 : DMA enable (1 = enabled)
Bits 6,5 : Preemt Count Select (transfers to complete after
'C01 has been preempted on MCA bus)
0 0 : 0
0 1 : 1
1 0 : 3
1 1 : 7
(all these wacky numbers; I'm sure there's a reason somewhere)
Bit 4 : Fairness enable (1 = fair bus priority)
Bits 3-0 : Arbitration level (0-15 consecutive)
Offset 4 : General purpose register
Bits 7-3 : User definable (here, 7,6 are SCSI ID)
Bits 2-0 : reserved
Offset 10 : DMA decode register (used for IO based DMA; also can do
PIO through this port)
Offset 12 : Status
Bits 7-2 : reserved
Bit 1 : DMA pending (1 = pending)
Bit 0 : IRQ pending (0 = pending)
Exciting, huh?"
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