Lola-2 seems to be a very interesting HDL and the Project Oberon (PO) FPGA implementation would be a good proof of concept.

But PO FPGA seems to be implemented in Verilog instead. I compared the Lola source files of Prof. Wirth's Risc5 (http://www-oldurls.inf.ethz.ch/personal/wirth/Lola/) with the current Verilog files (http://www.projectoberon.com/) and got the impression
that the Verilog version is independently developed (not translated with the Lola compiler) and more current. There seem to be evan a difference in between the syntax used in the Lola source files and the one specified in the language report. Also the
papers and book sections by Prof. Wirth only mention Verilog; there is one mention in the Xilinx journal article though.

Can someone comment on that? Is Lola-2 still in use and will it be further developed? What role does Lola-2 play in the PO FPGA project?

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On 2019-03-13 12:08, R.K. wrote:

Lola-2 seems to be a very interesting HDL and the Project Oberon (PO) FPGA implementation would be a good proof of concept.

But PO FPGA seems to be implemented in Verilog instead. I compared the Lola source files of Prof. Wirth's Risc5 (http://www-oldurls.inf.ethz.ch/personal/wirth/Lola/) with the current Verilog files (http://www.projectoberon.com/) and got the impression

that the Verilog version is independently developed (not translated with the Lola compiler) and more current. There seem to be evan a difference in between the syntax used in the Lola source files and the one specified in the language report. Also the
papers and book sections by Prof. Wirth only mention Verilog; there is one mention in the Xilinx journal article though.

Can someone comment on that? Is Lola-2 still in use and will it be further developed? What role does Lola-2 play in the PO FPGA project?

This newsgroup is for questions and discussions about the Oberon
programming language. You will probably get better feedback on the
Oberon mailing list at ETH Zürich:

https://lists.inf.ethz.ch/mailman/listinfo/oberon


-- August

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Ok, I see; thanks for the link, I will try there.
Can I conclude from your response that the FPGA version of Oberon system or the Lola-2 language (which looks very similar to Oberon) are not widely known among Oberon developers?

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, March 14, 2019 at 5:56:52 AM UTC+10:30, [email protected] wrote:

Ok, I see; thanks for the link, I will try there.
Can I conclude from your response that the FPGA version of Oberon system or the Lola-2 language (which looks very similar to Oberon) are not widely known among Oberon developers?

Not at all. However you might be able to conclude that this newsgroup is not widely known among current Oberon developers. There is *much* more activity on the ETH Oberon mailing list.

To answer your original question my understanding is that the Verilog files are the output from Lola-2. The latest version of the Lola-2 sources for the RISC5 softcore processor used in Project Oberon are dated Jan 2019. The Lola-2 language did have a
couple of recent revisions. The news.txt file on Wirth's site summarises these:

20190109 - Syntax change in Lola: Use "=" in (const and type) declarations;
use ":=" in statements (like in Oberon)

Regards,
Chris Burrows
CFB Software
http://www.astrobe.com/RISC5

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

The discussion continues here:

http://lists.inf.ethz.ch/pipermail/oberon/2019/013179.html

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)