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  • Generics Default vs.

    From Rick C@21:1/5 to All on Sun Sep 13 12:05:08 2020
    I use a generic to pass into the code a clock frequency as a real number in MHz. When an entity needs to measure time it can use that value to set clock counts. To make life simple (or maybe the opposite, not sure) I set a default for each entity...

    ENTITY Spkr_Drvr IS
    GENERIC (
    CLK_MHZ : REAL := 16.000
    );
    port(
    ...

    I don't recall what made me adopt this method. But I believe I encountered an instance where the generic was not passed in for whatever reason. I would expect that to be flagged as an error. But I expect it wasn't.

    Anyway, I would expect a value passed into an entity to take the value passed in and over ride the default value in the generic declaration. Is that what will happen? I will have at least two levels of this. If the top level gets a different value
    passed into it during simulation or in synthesis, will the value passed in take precedence?

    --

    Rick C.

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  • From Nicolas Matringe@21:1/5 to Rick C on Sun Sep 13 21:55:39 2020
    On 2020-09-13 21:05, Rick C wrote:
    [...]
    Anyway, I would expect a value passed into an entity to take the value passed in and over ride the default value in the generic declaration. Is that what will happen? I will have at least two levels of this. If the top level gets a different value
    passed into it during simulation or in synthesis, will the value passed in take precedence?


    The answer is pretty short and straightforward : yes.
    I've been using this method for years without any problem.

    Nicolas

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  • From Rick C@21:1/5 to Nicolas Matringe on Sun Sep 13 13:42:18 2020
    On Sunday, September 13, 2020 at 3:55:42 PM UTC-4, Nicolas Matringe wrote:
    On 2020-09-13 21:05, Rick C wrote:
    [...]
    Anyway, I would expect a value passed into an entity to take the value passed in and over ride the default value in the generic declaration. Is that what will happen? I will have at least two levels of this. If the top level gets a different value
    passed into it during simulation or in synthesis, will the value passed in take precedence?


    The answer is pretty short and straightforward : yes.
    I've been using this method for years without any problem.

    Nicolas

    Thanks,

    I've been doing this stuff for a long time, but not in the last couple of years or maybe more. I guess I'm forgetting a lot of details. I am spending a bunch of time online trying to find simpler ways to write what I want to do. I just tried to look
    up a way to do a conditional assignment in sequential code without an IF and without specifying the ELSE part since it should hold the value rather than change it. One really old reference (some university that took it down ages ago) says omitting the
    ELSE of a conditional signal assignment is "wrong". Another site shows an example of it. Of course they want to warn that it can cause instantiation of latches, but if it's already in a clocked process that ain't happenin'.

    It's times like these that I realize why people like Verilog. lol

    --

    Rick C.

    + Get 1,000 miles of free Supercharging
    + Tesla referral code - https://ts.la/richard11209

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