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  • VHDL'2019 is ratified !

    From Rob Gaddi@21:1/5 to HT-Lab on Thu Sep 19 09:58:59 2019
    On 9/19/19 8:01 AM, HT-Lab wrote:
    On 19/09/2019 15:01, Rick C wrote:
    On Monday, September 9, 2019 at 2:37:13 PM UTC-4, HT-Lab wrote:
    On 07/09/2019 13:38, [email protected] wrote:
    WOOOooooops ! Hans reported it yesterday :-D

    No problem, the more people report it the better.

    I don't believe VHDL2019 will kiss SV's (not Verilog's) ass but that is
    OK as it looks like VHDL2019 brings the 2 languages closer together
    (similar to what Accellera did with PSL and SVA).

    VHDL2019 will have DPI, interfaces and a preprocessor using the same
    unreadable "`" character as SV does :-(

    Hans
    www.ht-lab.com

    I don't know what that character is.  It doesn't seem to be the single quote
    "'".  I guess it is "`"...  Does that have a name?  Google seems to search on
    it ok.  It's called a "grave accent" and has uses in programing, also called
    "backquote" or "backtick".

    Yes, I know it from Verilog as the backtick but officially it is called a grave
    accent (also in the VHDL2019 LRM). I guess the steering group chose that character as it was already used for VHDL encryption and Verilog directives. Also with modern editors you quickly see if you are using the wrong character but still as an old C/ASM programmer I would have preferred '#'.


    I guess I vaguely recall seeing it on keyboards, but I don't recall ever using
    it for anything in my 45 year career, the only key on the keyboard like that I
    think... well, other than SYSRQ I guess.  I've at least played with SYSRQ to
    see what it does... nothing that I've ever found.


    I vaguely remember you posting that you prefer Verilog over VHDL so you must have used it many times? Perhaps like me your memory is not that great any more.

    Regards,
    Hans
    www.ht-lab.com



    Yep, it's a backtick. Also gets used a lot in shell scripting. I'm not sure if
    the reason to use it for the encryption directives in VHDL-2008 was that Verilog
    already uses it, but the decision to use it for other preprocessor sorts of things in VHDL-2019 was definitely driven by the fact that 2008 already "broke the seal" on it. Otherwise we'd have introduced yet another "everything henceforth is special magic" character. One of those is problematic enough, two
    is simply excessive.


    --
    Rob Gaddi, Highland Technology -- www.highlandtechnology.com
    Email address domain is currently out of order. See above to fix.

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  • From Rick C@21:1/5 to HT-Lab on Thu Sep 19 13:07:36 2019
    On Thursday, September 19, 2019 at 11:01:13 AM UTC-4, HT-Lab wrote:
    On 19/09/2019 15:01, Rick C wrote:
    On Monday, September 9, 2019 at 2:37:13 PM UTC-4, HT-Lab wrote:
    On 07/09/2019 13:38, [email protected] wrote:
    WOOOooooops ! Hans reported it yesterday :-D

    No problem, the more people report it the better.

    I don't believe VHDL2019 will kiss SV's (not Verilog's) ass but that is
    OK as it looks like VHDL2019 brings the 2 languages closer together
    (similar to what Accellera did with PSL and SVA).

    VHDL2019 will have DPI, interfaces and a preprocessor using the same
    unreadable "`" character as SV does :-(

    Hans
    www.ht-lab.com

    I don't know what that character is. It doesn't seem to be the single quote "'". I guess it is "`"... Does that have a name? Google seems to search on it ok. It's called a "grave accent" and has uses in programing, also called "backquote" or "
    backtick".

    Yes, I know it from Verilog as the backtick but officially it is called
    a grave accent (also in the VHDL2019 LRM). I guess the steering group
    chose that character as it was already used for VHDL encryption and
    Verilog directives. Also with modern editors you quickly see if you are using the wrong character but still as an old C/ASM programmer I would
    have preferred '#'.


    I guess I vaguely recall seeing it on keyboards, but I don't recall ever using it for anything in my 45 year career, the only key on the keyboard like that I think... well, other than SYSRQ I guess. I've at least played with SYSRQ to see what it
    does... nothing that I've ever found.


    I vaguely remember you posting that you prefer Verilog over VHDL so you
    must have used it many times? Perhaps like me your memory is not that
    great any more.

    No, the opposite. I know VHDL, I've only played with Verilog.

    --

    Rick C.

    -- Get 1,000 miles of free Supercharging
    -- Tesla referral code - https://ts.la/richard11209

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  • From [email protected]@21:1/5 to [email protected] on Thu Dec 5 14:33:49 2019
    On Saturday, September 7, 2019 at 6:35:11 AM UTC-6, [email protected] wrote:
    Jim Lewis shared the news :

    IEEE Std 1076-2019 has been approved by the IEEE SASB today.

    What a ride it was !

    I'm still frustrated by the crazy process and the refusal of my own tiny feature request but it's good to see that venerable language still moving forward and kicking Verilog's ass ;-)

    yg

    Maybe I can use it by the time I retire. Some customers still whine when I use Verilog-2005 because their tools won't parse such-and-such, so for synthesizable code, I pretty much have to stick to last century.

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