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  • Re: Instruction Parcel Size

    From MitchAlsup1@21:1/5 to Robert Finch on Sun Mar 9 01:43:07 2025
    On Sun, 9 Mar 2025 1:15:14 +0000, Robert Finch wrote:

    Recently started Q+2 development.

    Trying to get code density closer to something like the 68k or VAX.
    Sounds like My66000 also has good code density using 32-bit parcels. If 32-bit parcels work well, I have thought to try 24-bit parcels.

    Ok, go all Quadriblock on me .... see if I care !

    Decided to stay away from other odd sized parcels which create
    addressing issues. Currently 3 sizes of instructions: 24 / 48 and
    96-bit. The 96-bit instructions are usually for encoding a 64-bit
    immediate. The first two opcode bits determine the size. 00=24 bit,
    01=48 bit, 10=96 bit, 11 (reserved)

    You might find 72-bit instructions useful in carrying a 32-bit
    immediate.

    ADD, AND, OR, EOR, CMP have 24-bit instruction forms: iiiii-aaaaa-ttttt-ooooooo-00 <- immediate
    bbbbb-aaaaa-ttttt-ooooooo-00 <- register
    24-bit instruction forms allow using only the first 32 registers.

    A 6-bit OpCode might let 1 more bit into immediate, or similar
    sign control over register operand. Remember, this is the highly
    used OpCode category. So, we have 32 Imm5(6) OpCodes.

    ADD, AND, OR, EOR, CMP 48-bit instruction forms: fffffff-oooo-ccccccc-bbbbbbb-aaaaaaa-ttttttt-ooooooo-01
    48-bit instruction forms support a sign control bit on the register
    spec, along with 64 registers.

    It really looks like you are forming 2×24-bit instructions into
    (wait for it) 2×24-bit containers. Sign control on operands is
    useful 5-register operands may not be so. I am not against this
    format, but I think you are wasting a lot of entropy here.

    LOAD / STORE word size have 24-bit forms
    ddddd-aaaaa-ttttt-ooooooo-00

    Where do you get stack and structure displacements ?? This is one
    place My 66000 ISA is significantly better than RISC-V.

    Conditional Branches (compare and branch) are 48-bit pp-R-TTTTTTTTTTTTTTTTTTT-aaaaaa-bbbbbb-A-ffff-ooooooo-01

    Careful choice of oooooo may allow it to contain the condition
    in the ffff field expanding the displacement to 25-effective
    bits.

    With load / store / basic arithmetic as 24-bit and 48-bit
    compare-and-branch a good portion of instructions should occupy the same
    or less storage space than a 32-bit ISA.

    Questions remain wrt floating point constants and large integer
    constants.

    I have not written the assembler yet, so nothing to measure.

    The data will be interesting.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From MitchAlsup1@21:1/5 to Robert Finch on Sun Mar 9 18:09:22 2025
    On Sun, 9 Mar 2025 12:36:59 +0000, Robert Finch wrote:

    Conditional Branches (compare and branch) are 48-bit
    pp-R-TTTTTTTTTTTTTTTTTTT-aaaaaa-bbbbbb-A-ffff-ooooooo-01

    Careful choice of oooooo may allow it to contain the condition
    in the ffff field expanding the displacement to 25-effective
    bits.

    Gained a bit in the displacement field by allocating another row of
    opcodes and moving the 'R' bit into the opcode. So, now its

    pp-TTTTTTTTTTTTTTTTTTTT-aaaaaa-bbbbbb-A-ffff-oooRooo-01

    a longer form of branches could also be made using a 96-bit instruction

    pp-{68{T}}-aaaaaa-bbbbbb-A-ffff-oooRooo-10

    been pondering coming up with a shorter form (24-bit) branches, maybe by comparing to zero, BEQZ / BNEZ. Say,

    My 66000 uses 29 of the available 32 Conditions in the compare to
    zero and branch instruction. 6 signed integer, 4 unsigned integer,
    8 float, 8 double, and I stuck SVC, SVR, and RET in this instruction
    too.

    TTTTTTTTT-aaaaaa-ooooooo-00

    would be good only for word-size integer value comparisons, but that
    might work a significant portion of the time.

    Having 20 T's gives 21.5 bits of effective displacement, as the
    displacement T's are multiplied by three.

    Using up eight of the free opcodes, so there is only about 13 left now,
    but I think it was worth it to get a branch displacement bit.

    Hmmm, I could get rid of the 'A' bit by moving it to a control register.
    One would likely want absolute addressing for branches for the entire program, not just one-at-a-time selection.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)