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  • Re: Multics paging, Address bits again, Article on new mainframe use

    From Lawrence D'Oliveiro@21:1/5 to John Levine on Fri Sep 13 02:55:59 2024
    On Fri, 13 Sep 2024 02:16:42 -0000 (UTC), John Levine wrote:

    According to Lawrence D'Oliveiro <[email protected]d>:

    On Thu, 12 Sep 2024 21:26:01 -0000 (UTC), John Levine wrote:

    The other choice would have been a page table per segment, like
    Multics did.

    Remember that Multics segments all existed within a common, directly >>linearly-addressable address space.

    Sigh. Why guess wrong when it is so easy to look up the real answer?

    https://bitsavers.org/pdf/ge/GE-645/LSB0468_GE-645_System_Manual_Jan1968.pdf

    Nothing in there that contradicts what I’ve said.

    Note that segment sizes are 18 bits, while memory addresses are 24 bits.

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  • From John Levine@21:1/5 to All on Fri Sep 13 02:16:42 2024
    According to Lawrence D'Oliveiro <[email protected]d>:
    On Thu, 12 Sep 2024 21:26:01 -0000 (UTC), John Levine wrote:

    The other choice would have been a page table per segment, like Multics
    did.

    Remember that Multics segments all existed within a common, directly >linearly-addressable address space.

    Sigh. Why guess wrong when it is so easy to look up the real answer?

    https://bitsavers.org/pdf/ge/GE-645/LSB0468_GE-645_System_Manual_Jan1968.pdf

    A segment could be mapped into physical memory as a single unit, or it
    could be a sequence of 64 or 1024 word pages, with a page table saying
    where in physical memory each page was. It is my impression that most
    segments were paged, and the paged ones were mapped one page at a
    time, just like any other paging system.
    --
    Regards,
    John Levine, [email protected], Primary Perpetrator of "The Internet for Dummies",
    Please consider the environment before reading this e-mail. https://jl.ly

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