On Mon, 30 Oct 2023 21:24:22 +0000, Quadibloc wrote:

One mistake I had to correct: now, there is a lot less opcode space
available for headers, so I had to change the header format, not merely
go back to the earlier one.

Originally, I only modified the diagram of the header format. Now I
have also updated the text description of the header format on the
first page,

http://www.quadibloc.com/arch/ct17int.htm

John Savard

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On Tue, 31 Oct 2023 03:36:56 +0000, Quadibloc wrote:

Originally, I only modified the diagram of the header format. Now I have
also updated the text description of the header format on the first
page,

Another result of this latest round of changes is that the squeeze
on opcode space finally forced me to drop the "displaced instruction
header", which was that special header format I referred to earlier
which allowed a decode field to be indicated with essentially zero
overhead, by having a type of header which contained...

the decode field, required to allow pseudo-immediates, and
a position field, so that the instruction contained in this type of
header can be put between any two instruction slots in the remainder of
the block, and
an instruction.

The idea was to have eight 32-bit instructions in a block, and yet to
also have a decode field for pseudo-immediates.

John Savard

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On Tue, 31 Oct 2023 03:56:47 +0000, Quadibloc wrote:

Another result of this latest round of changes is that the squeeze on
opcode space finally forced me to drop the "displaced instruction
header",

That has been put back; now it's described with the header format,
instead of on the page on instruction formats, due to where I found the
opcode space for it.

However, now, not only is there no room for alternative condition code
sets, the opcode field is only seven bits long, so only the most basic
operate instructions may be inserted with immediates in this zero-overhead fashion. None the less, that is better than not having this way to
have pseudo-immediates without the overhead of reserving 32 bits for
a header.

John Savard

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On Friday, March 3, 2023 at 8:42:51 AM UTC-7, MitchAlsup wrote:

I feel that you are frustrated that you can't have your cake and eat it too.

Very definitely. So I have gone to a great deal of effort to squeeze the
opcode space so as to minimize the unavoidable compromises that come
from trying to have a full set of CISC addressing modes, plus banks of 32 registers as in a RISC architecture, with 32-bit instructions.

The reasons why I use block headers:

- to allow switching from the plain RISC decoding of every single instruction being exactly 32 bits long to allowing use of variable-length encodings while still allowing instructions to be decoded in parallel (just decode the header first, and you _immediately_ know where every instruction in the block is;

Yes, I know that it's possible to decode variable-length instructions quickly enough so that the benefits of this may be illusory;

- to allow immediate values to be used of every type and size without that burdening the scheme for decoding the lengths of instructions with excessive complexity.

Now, the point you made about a header being optimum for one implementation
is certainly a concern to me. I did believe that this was perhaps the greatest flaw
in the Itanium.

However, while the header format is indeed complicated, it still avoids one aspect
of the complexity of the Itanium. The block format is still simple like that of the
Texas Instruments DSP chips - all the instructions, except for the header, are the
same in any block.

So the ISA is still capable of a wide variety of implementations. It does not have
to be implemented in an 8-wide fashion. It can be implemented on a chip that fetches and decodes 32 instruction bits at a time, or one that fetches and decodes
128 bits at a time.

Or 512 bits at a time, although there provision has to be made for imposing serialization
between the two halves.

My goal has very definitely been to design an ISA that permits implementations in a wide variety of sizes, just like the IBM System/360. I don't achieve this quite as
well, but then the smaller sizes aren't used as much these days.

John Savard

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