I have a test fixture that uses RS-232 to communicate with a PC. It
actually uses the voltage levels of RS-232, even though this is from
a USB cable on the PC, so it's only RS-232 for maybe four inches.
lol
I'm redesigning the test fixtures to hold more units and fully
automate a few features that presently requires an operator. There
will now be 8 UUTs on each test fixture and I expect to have 10 to 20
test fixtures in a card rack. That's 80 to 160 UUTs total. There
will be an FPGA controlling each pair of UUTs, so 80 FPGAs in total
that the PC needs to talk to.
Rather than working on a way to mux 80 RS-232 interfaces, I'm
thinking it would be better to either daisy chain, or connect in
parallel all these devices. The protocol is master-slave where the
master sends a command and the slaves are idle until they reply. The
four FPGAs on a test fixture board could be connected in parallel
easily enough. But I don't think I want to run TTL level signals
between so many boards.
I could do an RS-422 interface with a master to slave pair and a
slave to master pair. The slaves do not speak until spoken to, so
there will be no collisions.
RS-485 would allow all this to be over a single pair of wires. But
the one big issue I see people complain about is getting PC software
to not clobber the slaves, or I should say, to get the master to wait
long enough that it's not clobbering it's own start bit by
overwriting the stop bit of the slave. I suppose someone, somewhere
has dealt with this on the PC and has a solution that doesn't impact
bus speed. I run the single test fixture version of this at about
100 kbps. I'm going to want as much speed as I can get for 80 FPGAs controlling 160 UUTs. Maybe I should give that some analysis,
because this might not be true.
The tests are of two types, most of them are setting up a state and
reading a signal. This can go pretty fast and doesn't take too many commands. Then there are the audio tests where the FPGA sends
digital data to the UUT, which does it's thing and returns digital
data which is crunched by the FPGA. This takes some small number of
seconds and presently the protocol is to poll the status until it is
done. That's a lot of messages, but it's not necessarily a slow
point. The same test can be started on every UUT in parallel, so the
waiting is in parallel. So maybe the serial port won't need to be
any faster.
Still, I want to use RS-422 or RS-485 to deal with ground noise since
this will be spread over multiple boards that don't have terribly
solid grounds, just the power cable really.
I'm thinking out loud here as much as anything. I intended to simply
ask if anyone had experience with RS-485 that would be helpful.
Running two wires rather than eight would be a help. I'll probably
use a 10 pin connector just to be on the safe side, allowing the
transceivers to be used either way.
On 02/11/2022 06:28, Rick C wrote:
RS-485 is easy from a PC using appropriate USB devices. We make heavy
use of FTDI's chips and cables - they handle the drive enables for the
RS-485 automatically so that from the PC side you just read and write to
the serial port.
The reception of the last byte from a slave is not finished until the
stop bit has been properly received by the master - that means at least half-way through the sending of the stop bit. Then there is a delay
before the data gets sent back to the host PC, a delay through the
kernel and drivers before it reaches the user program, time for the
program to handle that message, time for it to prepare the next message, delays through the kernel and drivers before it gets to the USB bus,
latency in the USB device that receives the USB message and then starts transmitting. There can be no collision unless all that delay is less
than half a bit time. And no matter how fast your computer is, you are always going to need at least one full USB polling cycle for all this,
which for USB 2.0 is 0.125 us. That means that if you have a baud rate
of 16 kbaud or higher, there is no possibility of a collision.
Il 02/11/2022 10:28, David Brown ha scritto:
On 02/11/2022 06:28, Rick C wrote:
RS-485 is easy from a PC using appropriate USB devices. We make heavy
use of FTDI's chips and cables - they handle the drive enables for the
RS-485 automatically so that from the PC side you just read and write
to the serial port.
The reception of the last byte from a slave is not finished until the
stop bit has been properly received by the master - that means at
least half-way through the sending of the stop bit. Then there is a
delay before the data gets sent back to the host PC, a delay through
the kernel and drivers before it reaches the user program, time for
the program to handle that message, time for it to prepare the next
message, delays through the kernel and drivers before it gets to the
USB bus, latency in the USB device that receives the USB message and
then starts transmitting. There can be no collision unless all that
delay is less than half a bit time. And no matter how fast your
computer is, you are always going to need at least one full USB
polling cycle for all this, which for USB 2.0 is 0.125 us. That means
that if you have a baud rate of 16 kbaud or higher, there is no
possibility of a collision.
However this depends on the speed of slave too, because it could be slow
to move *its* direction from TX to RX. If the master starts transmitting after the stop bit from the slave, but *before* it changes *its*
direction from TX to RX, the first bytes could be corrupted.
Unfortunately, not all UARTs in MCUs are able to drive automatically the
DE (Drive Enable) signal, so it sometimes happens that DE is a normal GPIO. If you are lucky, you have the TXC (transmit complete) interrupt that
fires *after* stop bit is transmitted, a safe time to move DE signal.
In this case interrupt delay is short, but you could have other active interrupts that occasionally could delay the TXC interrupt for some time.
On 02/11/2022 06:28, Rick C wrote:
I have a test fixture that uses RS-232 to communicate with a PC. It actually uses the voltage levels of RS-232, even though this is from
a USB cable on the PC, so it's only RS-232 for maybe four inches.
lol
I'm redesigning the test fixtures to hold more units and fully
automate a few features that presently requires an operator. There
will now be 8 UUTs on each test fixture and I expect to have 10 to 20
test fixtures in a card rack. That's 80 to 160 UUTs total. There
will be an FPGA controlling each pair of UUTs, so 80 FPGAs in total
that the PC needs to talk to.
Rather than working on a way to mux 80 RS-232 interfaces, I'm
thinking it would be better to either daisy chain, or connect in
parallel all these devices. The protocol is master-slave where the
master sends a command and the slaves are idle until they reply. The
four FPGAs on a test fixture board could be connected in parallel
easily enough. But I don't think I want to run TTL level signals
between so many boards.
I could do an RS-422 interface with a master to slave pair and a
slave to master pair. The slaves do not speak until spoken to, so
there will be no collisions.
RS-422 is normally a point-to-point interface. It is one line in each direction, but using balanced pairs instead of a TTL signal. You would
not normally connect multiple receivers or transmitters to an RS-422
bus, as the standard practice is that each transmitter is always driving
the pair it is attached to - there is no multi-drop.
RS-485 would allow all this to be over a single pair of wires. ButRS-485 is easy from a PC using appropriate USB devices. We make heavy
the one big issue I see people complain about is getting PC software
to not clobber the slaves, or I should say, to get the master to wait
long enough that it's not clobbering it's own start bit by
overwriting the stop bit of the slave. I suppose someone, somewhere
has dealt with this on the PC and has a solution that doesn't impact
bus speed. I run the single test fixture version of this at about
100 kbps. I'm going to want as much speed as I can get for 80 FPGAs controlling 160 UUTs. Maybe I should give that some analysis,
because this might not be true.
use of FTDI's chips and cables - they handle the drive enables for the RS-485 automatically so that from the PC side you just read and write to
the serial port.
The reception of the last byte from a slave is not finished until the
stop bit has been properly received by the master - that means at least half-way through the sending of the stop bit.
Then there is a delay
before the data gets sent back to the host PC, a delay through the
kernel and drivers before it reaches the user program, time for the
program to handle that message, time for it to prepare the next message, delays through the kernel and drivers before it gets to the USB bus,
latency in the USB device that receives the USB message and then starts transmitting. There can be no collision unless all that delay is less
than half a bit time. And no matter how fast your computer is, you are always going to need at least one full USB polling cycle for all this,
which for USB 2.0 is 0.125 us. That means that if you have a baud rate
of 16 kbaud or higher, there is no possibility of a collision.
The tests are of two types, most of them are setting up a state and reading a signal. This can go pretty fast and doesn't take too many commands. Then there are the audio tests where the FPGA sends
digital data to the UUT, which does it's thing and returns digital
data which is crunched by the FPGA. This takes some small number of seconds and presently the protocol is to poll the status until it is
done. That's a lot of messages, but it's not necessarily a slow
point. The same test can be started on every UUT in parallel, so the waiting is in parallel. So maybe the serial port won't need to be
any faster.
Still, I want to use RS-422 or RS-485 to deal with ground noise since
this will be spread over multiple boards that don't have terribly
solid grounds, just the power cable really.
I'm thinking out loud here as much as anything. I intended to simply
ask if anyone had experience with RS-485 that would be helpful.
Running two wires rather than eight would be a help. I'll probably
use a 10 pin connector just to be on the safe side, allowing the transceivers to be used either way.
You need to do some calculations to see if you can get enough telegrams
and enough data through a single serial port. You'll be hard pushed to
find a USB serial port device of any kind that goes above 3 Mbaud, and
you need to be careful about your selection of RS-485 drivers for those kinds of rates. You will also find that much of your bandwidth is taken
up with pauses between telegrams and reply latency, unless you make your telegrams quite large.
When we have made testbenches that required serial communication to
multiple parallel devices, we typically put a USB hub in the testbench
and use multiple FDTI USB to serial cables. You only make one (or
possibly a few) of the testbenches - it's much cheaper to use
off-the-shelf parts than to spend time designing something more
advanced. You can buy a /lot/ of hubs and USB cables for the price of
the time to design, build and program a custom card for the job. It
also makes the system more scalable, as the communication to different devices runs in parallel.
We have also done systems where there is a Raspberry Pi driving the hub
and multiple FTDI converters. The PC is connected to the Pi by Ethernet (useful for galvanic isolation), and the Pi runs forwarders between the serial ports and TCP/IP ports.
To be fair, I don't recall any testbenches we've made that needed more
than perhaps 8 serial ports. If I needed to handle 80 lines, I would probably split things up - a Pi handling 8-10 lines from a local
program, communicating with a PC master program by Ethernet.
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown
wrote:
On 02/11/2022 06:28, Rick C wrote:
I have a test fixture that uses RS-232 to communicate with a PC.RS-422 is normally a point-to-point interface. It is one line in
It actually uses the voltage levels of RS-232, even though this
is from a USB cable on the PC, so it's only RS-232 for maybe four
inches. lol
I'm redesigning the test fixtures to hold more units and fully
automate a few features that presently requires an operator.
There will now be 8 UUTs on each test fixture and I expect to
have 10 to 20 test fixtures in a card rack. That's 80 to 160 UUTs
total. There will be an FPGA controlling each pair of UUTs, so 80
FPGAs in total that the PC needs to talk to.
Rather than working on a way to mux 80 RS-232 interfaces, I'm
thinking it would be better to either daisy chain, or connect in
parallel all these devices. The protocol is master-slave where
the master sends a command and the slaves are idle until they
reply. The four FPGAs on a test fixture board could be connected
in parallel easily enough. But I don't think I want to run TTL
level signals between so many boards.
I could do an RS-422 interface with a master to slave pair and a
slave to master pair. The slaves do not speak until spoken to,
so there will be no collisions.
each direction, but using balanced pairs instead of a TTL signal.
You would not normally connect multiple receivers or transmitters
to an RS-422 bus, as the standard practice is that each transmitter
is always driving the pair it is attached to - there is no
multi-drop.
That is simply not true. Data sheets for RS-422 devices often show
multidrop applications and how to best terminate them.
RS-485 would allow all this to be over a single pair of wires.RS-485 is easy from a PC using appropriate USB devices. We make
But the one big issue I see people complain about is getting PC
software to not clobber the slaves, or I should say, to get the
master to wait long enough that it's not clobbering it's own
start bit by overwriting the stop bit of the slave. I suppose
someone, somewhere has dealt with this on the PC and has a
solution that doesn't impact bus speed. I run the single test
fixture version of this at about 100 kbps. I'm going to want as
much speed as I can get for 80 FPGAs controlling 160 UUTs. Maybe
I should give that some analysis, because this might not be
true.
heavy use of FTDI's chips and cables - they handle the drive
enables for the RS-485 automatically so that from the PC side you
just read and write to the serial port.
I've yet to be convinced of this. Admittedly, my last interaction
with RS-485 was many years ago, but there were some four or five
different devices being integrated with a PC, and no two of them
handled it the bus the same way. The PC in particular, would cut on
and off the driver in the middle of bits. No one put a bias on the
bus, so it was indeterminate when no one was driving. It was a
horrible failure.
Every time I've seen this discussed, the driver control has been an
issue.
The reception of the last byte from a slave is not finished until
the stop bit has been properly received by the master - that means
at least half-way through the sending of the stop bit.
That's not sufficient. Everyone's halfway is a bit different and
start bit detection may not be enabled on some device when the next
driver outputs a start bit, or the last driver may not be turned off
when the next driver starts.
Then there is a delay before the data gets sent back to the host
PC, a delay through the kernel and drivers before it reaches the
user program, time for the program to handle that message, time for
it to prepare the next message, delays through the kernel and
drivers before it gets to the USB bus, latency in the USB device
that receives the USB message and then starts transmitting. There
can be no collision unless all that delay is less than half a bit
time. And no matter how fast your computer is, you are always going
to need at least one full USB polling cycle for all this, which for
USB 2.0 is 0.125 us. That means that if you have a baud rate of 16
kbaud or higher, there is no possibility of a collision.
If your numbers are accurate, that might be ok, but I'm looking for
data rates closer to 1 Mbps.
Admittedly, I have not done an analysis
of what will actually be required, but 128 UUT, or possibly 256, can
do a lot of damage to a shared bus. At 1 Mbps, 128 UUT results in an effective bit rate maximum of 7.8 kbps. With 256 UUTs, that's 3.9
kbps. No, I don't think this will work properly at much slower
speeds than 1 Mbps. At 16 kbps, the effective rate to each UUT is
just 62.5 bps, not kbps.
The tests are of two types, most of them are setting up a stateYou need to do some calculations to see if you can get enough
and reading a signal. This can go pretty fast and doesn't take
too many commands. Then there are the audio tests where the FPGA
sends digital data to the UUT, which does it's thing and returns
digital data which is crunched by the FPGA. This takes some small
number of seconds and presently the protocol is to poll the
status until it is done. That's a lot of messages, but it's not
necessarily a slow point. The same test can be started on every
UUT in parallel, so the waiting is in parallel. So maybe the
serial port won't need to be any faster.
Still, I want to use RS-422 or RS-485 to deal with ground noise
since this will be spread over multiple boards that don't have
terribly solid grounds, just the power cable really.
I'm thinking out loud here as much as anything. I intended to
simply ask if anyone had experience with RS-485 that would be
helpful. Running two wires rather than eight would be a help.
I'll probably use a 10 pin connector just to be on the safe side,
allowing the transceivers to be used either way.
telegrams and enough data through a single serial port. You'll be
hard pushed to find a USB serial port device of any kind that goes
above 3 Mbaud, and you need to be careful about your selection of
RS-485 drivers for those kinds of rates. You will also find that
much of your bandwidth is taken up with pauses between telegrams
and reply latency, unless you make your telegrams quite large.
I assume by "telegrams", you mean the messages. They will be small
by necessity. The protocol is interactive with a command message and
a reply message. Read a register, write a register.
When we have made testbenches that required serial communication
to multiple parallel devices, we typically put a USB hub in the
testbench and use multiple FDTI USB to serial cables. You only make
one (or possibly a few) of the testbenches - it's much cheaper to
use off-the-shelf parts than to spend time designing something
more advanced. You can buy a /lot/ of hubs and USB cables for the
price of the time to design, build and program a custom card for
the job. It also makes the system more scalable, as the
communication to different devices runs in parallel.
USB hubs are a last resort. I've found many issues with such
devices, especially larger than 4 ports.
We have also done systems where there is a Raspberry Pi driving the
hub and multiple FTDI converters. The PC is connected to the Pi by
Ethernet (useful for galvanic isolation), and the Pi runs
forwarders between the serial ports and TCP/IP ports.
There is a possibility of using an rPi on an Ethernet cable to the PC
with direct comms to each test fixture board, but that's more work
that I'm interested in.
To be fair, I don't recall any testbenches we've made that needed
more than perhaps 8 serial ports. If I needed to handle 80 lines, I
would probably split things up - a Pi handling 8-10 lines from a
local program, communicating with a PC master program by Ethernet.
That's the advantage of the shared bus. No programming required,
other than extending the protocol to move from "selecting" a device
on the FPGA, to selecting the FPGA as well.
That's 80 to 160 UUTs total. There will be an FPGA controlling each
pair of UUTs, so 80 FPGAs in total that the PC needs to talk to.
On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown
wrote:
On 02/11/2022 06:28, Rick C wrote:
I have a test fixture that uses RS-232 to communicate with a PC.RS-422 is normally a point-to-point interface. It is one line in
It actually uses the voltage levels of RS-232, even though this
is from a USB cable on the PC, so it's only RS-232 for maybe four
inches. lol
I'm redesigning the test fixtures to hold more units and fully
automate a few features that presently requires an operator.
There will now be 8 UUTs on each test fixture and I expect to
have 10 to 20 test fixtures in a card rack. That's 80 to 160 UUTs
total. There will be an FPGA controlling each pair of UUTs, so 80
FPGAs in total that the PC needs to talk to.
Rather than working on a way to mux 80 RS-232 interfaces, I'm
thinking it would be better to either daisy chain, or connect in
parallel all these devices. The protocol is master-slave where
the master sends a command and the slaves are idle until they
reply. The four FPGAs on a test fixture board could be connected
in parallel easily enough. But I don't think I want to run TTL
level signals between so many boards.
I could do an RS-422 interface with a master to slave pair and a
slave to master pair. The slaves do not speak until spoken to,
so there will be no collisions.
each direction, but using balanced pairs instead of a TTL signal.
You would not normally connect multiple receivers or transmitters
to an RS-422 bus, as the standard practice is that each transmitter
is always driving the pair it is attached to - there is no
multi-drop.
That is simply not true. Data sheets for RS-422 devices often show multidrop applications and how to best terminate them.
RS-422 is not multidrop. Occasionally you will see multiple receivers
on a bus, but not multiple transmitters.
Of course the same driver chips can be used in different combinations of wiring and drive enables. An RS-422 driver chip can be viewed as two
RS-485 driver chips - alternatively, a RS-485 driver can be viewed as an RS-422 driver with the two differential pairs connected together.
Really, all you are talking about is a differential driver and a differential receiver.
So yes, you can do multidrop using an RS-422 driver chip. But it is not RS-422, which is a point-to-point serial bus standard.
RS-485 would allow all this to be over a single pair of wires.RS-485 is easy from a PC using appropriate USB devices. We make
But the one big issue I see people complain about is getting PC
software to not clobber the slaves, or I should say, to get the
master to wait long enough that it's not clobbering it's own
start bit by overwriting the stop bit of the slave. I suppose
someone, somewhere has dealt with this on the PC and has a
solution that doesn't impact bus speed. I run the single test
fixture version of this at about 100 kbps. I'm going to want as
much speed as I can get for 80 FPGAs controlling 160 UUTs. Maybe
I should give that some analysis, because this might not be
true.
heavy use of FTDI's chips and cables - they handle the drive
enables for the RS-485 automatically so that from the PC side you
just read and write to the serial port.
I've yet to be convinced of this. Admittedly, my last interaction
with RS-485 was many years ago, but there were some four or five
different devices being integrated with a PC, and no two of them
handled it the bus the same way. The PC in particular, would cut on
and off the driver in the middle of bits. No one put a bias on the
bus, so it was indeterminate when no one was driving. It was a
horrible failure.
Every time I've seen this discussed, the driver control has been anI can tell you it works perfectly with FTDI's RS-485 cables - every
issue.
time, every OS, regardless of the software. Some RS-485 drivers rely on
RTS for the drive enable - this was the standard for RS-232 to RS-485 converters from the old days of 9-pin and 25-pin serial ports on PC's.
With such drivers, it is certainly possible to get things wrong. With
the drive enable handled directly by the UART hardware on the USB chip,
it is /far/ harder to get it wrong.
I would expect there to be many alternatives to FTDI that work similarly well, but that's the ones we generally use.
<https://ftdichip.com/product-category/products/cables/?series_products=55>
The reception of the last byte from a slave is not finished until
the stop bit has been properly received by the master - that means
at least half-way through the sending of the stop bit.
That's not sufficient. Everyone's halfway is a bit different and
start bit detection may not be enabled on some device when the next
driver outputs a start bit, or the last driver may not be turned off
when the next driver starts.
"At least half-way" means "at least 50% of the bit time". As long as
the start bit from the next message is not sent until at least 50% of a
bit time after the stop bit is detected, it will not conflict and all listening devices will be ready to see the start bit. (Devices that
needed two stop bits haven't existed in the last 50 years.)
You asked specifically about bus turnaround at the host side - I assume
that is because on the slave devices, you have control of the drive
enables and bus turnaround happens with negligible latency.
Then there is a delay before the data gets sent back to the host
PC, a delay through the kernel and drivers before it reaches the
user program, time for the program to handle that message, time for
it to prepare the next message, delays through the kernel and
drivers before it gets to the USB bus, latency in the USB device
that receives the USB message and then starts transmitting. There
can be no collision unless all that delay is less than half a bit
time. And no matter how fast your computer is, you are always going
to need at least one full USB polling cycle for all this, which for
USB 2.0 is 0.125 us. That means that if you have a baud rate of 16
kbaud or higher, there is no possibility of a collision.
If your numbers are accurate, that might be ok, but I'm looking forUSB serial ports generally use the 48 MHz base USB reference frequency
data rates closer to 1 Mbps.
as their source clock to scale down by a baud rate divisor, and common practice is 16 sub-bit clocks per line bit (so that you can have
multiple samples for noise immunity). Thus baud rates of integer
divisions of 3 MBaud are common. Certainly the FTDI chips handle 1, 2
and 3 MBaud. (I haven't had need of such speeds with RS-485, but have happily used the common 3v3 TTL cables at 3 MBaud.)
Admittedly, I have not done an analysis
of what will actually be required, but 128 UUT, or possibly 256, can
do a lot of damage to a shared bus. At 1 Mbps, 128 UUT results in an effective bit rate maximum of 7.8 kbps. With 256 UUTs, that's 3.9
kbps. No, I don't think this will work properly at much slower
speeds than 1 Mbps. At 16 kbps, the effective rate to each UUT is
just 62.5 bps, not kbps.
As long as you are /above/ 16 kbaud, you should be fine (at the PC
side). At 1 Mbaud, you do not need to worry about the PC starting a new telegram before the last received stop bit is completed.
The tests are of two types, most of them are setting up a stateYou need to do some calculations to see if you can get enough
and reading a signal. This can go pretty fast and doesn't take
too many commands. Then there are the audio tests where the FPGA
sends digital data to the UUT, which does it's thing and returns
digital data which is crunched by the FPGA. This takes some small
number of seconds and presently the protocol is to poll the
status until it is done. That's a lot of messages, but it's not
necessarily a slow point. The same test can be started on every
UUT in parallel, so the waiting is in parallel. So maybe the
serial port won't need to be any faster.
Still, I want to use RS-422 or RS-485 to deal with ground noise
since this will be spread over multiple boards that don't have
terribly solid grounds, just the power cable really.
I'm thinking out loud here as much as anything. I intended to
simply ask if anyone had experience with RS-485 that would be
helpful. Running two wires rather than eight would be a help.
I'll probably use a 10 pin connector just to be on the safe side,
allowing the transceivers to be used either way.
telegrams and enough data through a single serial port. You'll be
hard pushed to find a USB serial port device of any kind that goes
above 3 Mbaud, and you need to be careful about your selection of
RS-485 drivers for those kinds of rates. You will also find that
much of your bandwidth is taken up with pauses between telegrams
and reply latency, unless you make your telegrams quite large.
I assume by "telegrams", you mean the messages. They will be small
by necessity. The protocol is interactive with a command message and
a reply message. Read a register, write a register.
Telegram, message, packet - whatever term you prefer. At faster baud
rates, the inevitable pauses between messages take proportionately more
of the total bandwidth. Longer messages will be more efficient. But
you'll have to do the sums yourself to see what rates you need, and
whether or not this will be an issue.
When we have made testbenches that required serial communication
to multiple parallel devices, we typically put a USB hub in the
testbench and use multiple FDTI USB to serial cables. You only make
one (or possibly a few) of the testbenches - it's much cheaper to
use off-the-shelf parts than to spend time designing something
more advanced. You can buy a /lot/ of hubs and USB cables for the
price of the time to design, build and program a custom card for
the job. It also makes the system more scalable, as the
communication to different devices runs in parallel.
USB hubs are a last resort. I've found many issues with such
devices, especially larger than 4 ports.
We find they work fine - I have very rarely seen any issues with off-the-shelf hubs, regardless of the number of ports. (They are almost
all made with 1-to-4 hub chips, which is why hubs are often found in
sizes of 4 ports, 7 ports, or 10 ports.)
A key complication with multiple serial ports on hubs is if you are
using Windows, it can be a big pain to keep consistent numbering for the serial ports. You may have to use driver-specific libraries (like
FTDI's DLL's) to check serial numbers and use that information. It's
far easier on Linux where you can make a udev configuration file that
gives aliases to your ports ordered by physical tree address.
We have also done systems where there is a Raspberry Pi driving the
hub and multiple FTDI converters. The PC is connected to the Pi by
Ethernet (useful for galvanic isolation), and the Pi runs
forwarders between the serial ports and TCP/IP ports.
There is a possibility of using an rPi on an Ethernet cable to the PC
with direct comms to each test fixture board, but that's more work
that I'm interested in.
Or you could use one Pi for a set of boards - whatever is physically convenient.
To be fair, I don't recall any testbenches we've made that needed
more than perhaps 8 serial ports. If I needed to handle 80 lines, I
would probably split things up - a Pi handling 8-10 lines from a
local program, communicating with a PC master program by Ethernet.
That's the advantage of the shared bus. No programming required,
other than extending the protocol to move from "selecting" a device
on the FPGA, to selecting the FPGA as well.
If you are familiar with socat, the Pi doesn't necessarily need any programming either. (In our case we wanted some extra monitoring and logging, which was more than we could get from socat - so it was a
couple of hundred lines of Python in the end.)
Rick C <[email protected]> writes:
That's 80 to 160 UUTs total. There will be an FPGA controlling eachRather than make a huge shared bus, I wonder if you could move the test controller from a PC to a small microprocessor board that controls two FPGA's or whatever. Then use a bunch of separate boards of that type, communicating with a PC using some method that doesn't have to be
pair of UUTs, so 80 FPGAs in total that the PC needs to talk to.
especially fast. The microprocessor board could be something like a Raspberry Pi Pico, which costs $4 and can run Mecrisp, if that is what
your software is written with. It is quite a powerful little board.
I'm lost. How is this any better? The data collection is running on
the PC, so there still has to be communications... All they would be
doing is acting as a serial port concentrator. They went out 40 years
ago!
Rick C <[email protected]> writes:
I'm lost. How is this any better? The data collection is running onWell, I always like doing stuff in software instead of hardware.
the PC, so there still has to be communications... All they would be
doing is acting as a serial port concentrator. They went out 40 years
ago!
Serial
port concentrators are still around and I posted a link to one in your
other thread. It seems like a reasonable approach too. Oddly, a quick
web search doesn't find any big cheap serial to ethernet ones, but maybe
you could use USB hubs and FTDI-like cables.
The idea of using an MCU is to move almost everything speed critical
away from the PC. The MCU only has control the FPGA's and transfer
transfer digested data upwards to the PC. By having some fanout you
could potentially control 1000s of UUT instead of 80 from a single PC, without having to build anything special. It would just mean plugging
some off the shelf boxes together, and writing some code.
You're more comfortable with hardware than I am, so maybe that approach
has less attraction for you than it does for me.
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown wrote:signaling, with unidirectional/non-reversible, terminated or non-terminated transmission lines, point to point, or multi-drop. In contrast to EIA-485, RS-422/V.11 does not allow multiple drivers but only multiple receivers."
On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David BrownRS-422 is not multidrop. Occasionally you will see multiple receivers
wrote:
On 02/11/2022 06:28, Rick C wrote:
I have a test fixture that uses RS-232 to communicate with a PC.RS-422 is normally a point-to-point interface. It is one line in
It actually uses the voltage levels of RS-232, even though this
is from a USB cable on the PC, so it's only RS-232 for maybe four
inches. lol
I'm redesigning the test fixtures to hold more units and fully
automate a few features that presently requires an operator.
There will now be 8 UUTs on each test fixture and I expect to
have 10 to 20 test fixtures in a card rack. That's 80 to 160 UUTs
total. There will be an FPGA controlling each pair of UUTs, so 80
FPGAs in total that the PC needs to talk to.
Rather than working on a way to mux 80 RS-232 interfaces, I'm
thinking it would be better to either daisy chain, or connect in
parallel all these devices. The protocol is master-slave where
the master sends a command and the slaves are idle until they
reply. The four FPGAs on a test fixture board could be connected
in parallel easily enough. But I don't think I want to run TTL
level signals between so many boards.
I could do an RS-422 interface with a master to slave pair and a
slave to master pair. The slaves do not speak until spoken to,
so there will be no collisions.
each direction, but using balanced pairs instead of a TTL signal.
You would not normally connect multiple receivers or transmitters
to an RS-422 bus, as the standard practice is that each transmitter
is always driving the pair it is attached to - there is no
multi-drop.
That is simply not true. Data sheets for RS-422 devices often show
multidrop applications and how to best terminate them.
on a bus, but not multiple transmitters.
Not sure of your point. Multi-drop is multiple receivers on a single transmitter. Multi-point is multiple drivers and receivers. Look at a few references. Even wikipedia says, "RS-422 provides for data transmission, using balanced, or differential,
Of course the same driver chips can be used in different combinations of
wiring and drive enables. An RS-422 driver chip can be viewed as two
RS-485 driver chips - alternatively, a RS-485 driver can be viewed as an
RS-422 driver with the two differential pairs connected together.
Really, all you are talking about is a differential driver and a
differential receiver.
Sure, but the point is, nothing in RS-422 precludes multiple receivers, and in fact, every reference I've found (not paying for the actual spec) shows multi-drop receivers.
from the standard itself.So yes, you can do multidrop using an RS-422 driver chip. But it is not
RS-422, which is a point-to-point serial bus standard.
I don't believe that is correct. If you have a copy of the spec to share, I'd love to look at it. I might have one myself, but it would be a paper copy somewhere unknown. The diagrams showing multi-drop RS-422 is so ubiquitous, I expect they are
end* of the stop bit of the transmitted character. Knowing when it is ok to enable the driver has the same problem. The data is "received" in the middle of the stop bit. So the enable has to be a half bit time later, at the end of the stop bit.I can tell you it works perfectly with FTDI's RS-485 cables - everyRS-485 would allow all this to be over a single pair of wires.RS-485 is easy from a PC using appropriate USB devices. We make
But the one big issue I see people complain about is getting PC
software to not clobber the slaves, or I should say, to get the
master to wait long enough that it's not clobbering it's own
start bit by overwriting the stop bit of the slave. I suppose
someone, somewhere has dealt with this on the PC and has a
solution that doesn't impact bus speed. I run the single test
fixture version of this at about 100 kbps. I'm going to want as
much speed as I can get for 80 FPGAs controlling 160 UUTs. Maybe
I should give that some analysis, because this might not be
true.
heavy use of FTDI's chips and cables - they handle the drive
enables for the RS-485 automatically so that from the PC side you
just read and write to the serial port.
I've yet to be convinced of this. Admittedly, my last interaction
with RS-485 was many years ago, but there were some four or five
different devices being integrated with a PC, and no two of them
handled it the bus the same way. The PC in particular, would cut on
and off the driver in the middle of bits. No one put a bias on the
bus, so it was indeterminate when no one was driving. It was a
horrible failure.
Every time I've seen this discussed, the driver control has been an
issue.
time, every OS, regardless of the software. Some RS-485 drivers rely on
RTS for the drive enable - this was the standard for RS-232 to RS-485
converters from the old days of 9-pin and 25-pin serial ports on PC's.
With such drivers, it is certainly possible to get things wrong. With
the drive enable handled directly by the UART hardware on the USB chip,
it is /far/ harder to get it wrong.
So, what range of speeds have you used? It is actually the UART hardware that *does* get it very wrong by working off the transmitter empty signal, which changes in the middle of the bit. The control has to be specially designed to transition at the *
None of this matters to me really. I'm going to use more wires, and do the multi-drop from the PC to the slaves on one pair and use RS-422 to multi-point from the slaves to the PC. Since the slaves are controlled by the master, they will nevercollide. The master can't collide with itself, so I can ignore any issues with this. I will use the bias resistors to assure a valid idle state. I may need to select different devices than the ones I use in the product. I think there are differences
guaranteed. That's why they call it "asynchronous" serial.I would expect there to be many alternatives to FTDI that work similarly
well, but that's the ones we generally use.
<https://ftdichip.com/product-category/products/cables/?series_products=55> >>>
"At least half-way" means "at least 50% of the bit time". As long asThe reception of the last byte from a slave is not finished until
the stop bit has been properly received by the master - that means
at least half-way through the sending of the stop bit.
That's not sufficient. Everyone's halfway is a bit different and
start bit detection may not be enabled on some device when the next
driver outputs a start bit, or the last driver may not be turned off
when the next driver starts.
the start bit from the next message is not sent until at least 50% of a
bit time after the stop bit is detected, it will not conflict and all
listening devices will be ready to see the start bit. (Devices that
needed two stop bits haven't existed in the last 50 years.)
You don't seem to understand that there is nothing timing from the start of the bit. The timing is from the first detected low of the start bit. From there, all timing is done by an internal clock. Check the math, you don't get 50% of the stop bit,
though, but early is the easy way and generally doesn't cause a problem. The master has trouble on both ends of it's message, needing to be careful to not turn on the driver too soon and not turning it off too late to clobber the reply.You asked specifically about bus turnaround at the host side - I assume
that is because on the slave devices, you have control of the drive
enables and bus turnaround happens with negligible latency.
I know the master has the most trouble with this. The slaves tend to not have a problem because they are operated by MCUs and can wait a bit time before replying, or even a character time. I suppose they don't have any magic on turning off the driver
USB serial ports generally use the 48 MHz base USB reference frequencyThen there is a delay before the data gets sent back to the host
PC, a delay through the kernel and drivers before it reaches the
user program, time for the program to handle that message, time for
it to prepare the next message, delays through the kernel and
drivers before it gets to the USB bus, latency in the USB device
that receives the USB message and then starts transmitting. There
can be no collision unless all that delay is less than half a bit
time. And no matter how fast your computer is, you are always going
to need at least one full USB polling cycle for all this, which for
USB 2.0 is 0.125 us. That means that if you have a baud rate of 16
kbaud or higher, there is no possibility of a collision.
If your numbers are accurate, that might be ok, but I'm looking for
data rates closer to 1 Mbps.
as their source clock to scale down by a baud rate divisor, and common
practice is 16 sub-bit clocks per line bit (so that you can have
multiple samples for noise immunity). Thus baud rates of integer
divisions of 3 MBaud are common. Certainly the FTDI chips handle 1, 2
and 3 MBaud. (I haven't had need of such speeds with RS-485, but have
happily used the common 3v3 TTL cables at 3 MBaud.)
At some point you have to worry with the line waveforms. So too fast can cause problems when using *lots* of receivers.
Admittedly, I have not done an analysisAs long as you are /above/ 16 kbaud, you should be fine (at the PC
of what will actually be required, but 128 UUT, or possibly 256, can
do a lot of damage to a shared bus. At 1 Mbps, 128 UUT results in an
effective bit rate maximum of 7.8 kbps. With 256 UUTs, that's 3.9
kbps. No, I don't think this will work properly at much slower
speeds than 1 Mbps. At 16 kbps, the effective rate to each UUT is
just 62.5 bps, not kbps.
side). At 1 Mbaud, you do not need to worry about the PC starting a new
telegram before the last received stop bit is completed.
Not entirely. The master has to turn *off* the driver before the slave replies. At higher speeds that's a problem. But it all depends on how it is being done. This is why I'm going with two busses, one for master transmit and one for master input.
interface to the UUT is serial, at 30 MHz and the turn around is so quick, I had to use a mux to select the first bit and shift the rest of the data from a shift register. All in all it is under a μs for a transfer, and the data can be sent to the PCTelegram, message, packet - whatever term you prefer. At faster baudThe tests are of two types, most of them are setting up a stateYou need to do some calculations to see if you can get enough
and reading a signal. This can go pretty fast and doesn't take
too many commands. Then there are the audio tests where the FPGA
sends digital data to the UUT, which does it's thing and returns
digital data which is crunched by the FPGA. This takes some small
number of seconds and presently the protocol is to poll the
status until it is done. That's a lot of messages, but it's not
necessarily a slow point. The same test can be started on every
UUT in parallel, so the waiting is in parallel. So maybe the
serial port won't need to be any faster.
Still, I want to use RS-422 or RS-485 to deal with ground noise
since this will be spread over multiple boards that don't have
terribly solid grounds, just the power cable really.
I'm thinking out loud here as much as anything. I intended to
simply ask if anyone had experience with RS-485 that would be
helpful. Running two wires rather than eight would be a help.
I'll probably use a 10 pin connector just to be on the safe side,
allowing the transceivers to be used either way.
telegrams and enough data through a single serial port. You'll be
hard pushed to find a USB serial port device of any kind that goes
above 3 Mbaud, and you need to be careful about your selection of
RS-485 drivers for those kinds of rates. You will also find that
much of your bandwidth is taken up with pauses between telegrams
and reply latency, unless you make your telegrams quite large.
I assume by "telegrams", you mean the messages. They will be small
by necessity. The protocol is interactive with a command message and
a reply message. Read a register, write a register.
rates, the inevitable pauses between messages take proportionately more
of the total bandwidth. Longer messages will be more efficient. But
you'll have to do the sums yourself to see what rates you need, and
whether or not this will be an issue.
Not sure what delays you are talking about. Every message is either selecting a slave, or reading a register or writing a register. You are probably thinking like a code banger where you have to worry with software delays. The protocol at the
We find they work fine - I have very rarely seen any issues withWhen we have made testbenches that required serial communication
to multiple parallel devices, we typically put a USB hub in the
testbench and use multiple FDTI USB to serial cables. You only make
one (or possibly a few) of the testbenches - it's much cheaper to
use off-the-shelf parts than to spend time designing something
more advanced. You can buy a /lot/ of hubs and USB cables for the
price of the time to design, build and program a custom card for
the job. It also makes the system more scalable, as the
communication to different devices runs in parallel.
USB hubs are a last resort. I've found many issues with such
devices, especially larger than 4 ports.
off-the-shelf hubs, regardless of the number of ports. (They are almost
all made with 1-to-4 hub chips, which is why hubs are often found in
sizes of 4 ports, 7 ports, or 10 ports.)
Exactly, and I find combining them like that has issues.
A key complication with multiple serial ports on hubs is if you are
using Windows, it can be a big pain to keep consistent numbering for the
serial ports. You may have to use driver-specific libraries (like
FTDI's DLL's) to check serial numbers and use that information. It's
far easier on Linux where you can make a udev configuration file that
gives aliases to your ports ordered by physical tree address.
Yet another reason to avoid such complications. The reality is there's no gain. The multi-drop is the right way to go here.
rPis. Last time I checked, it was hard to find rPis. They are part of the unobtainium universe now, it seems.Or you could use one Pi for a set of boards - whatever is physicallyWe have also done systems where there is a Raspberry Pi driving the
hub and multiple FTDI converters. The PC is connected to the Pi by
Ethernet (useful for galvanic isolation), and the Pi runs
forwarders between the serial ports and TCP/IP ports.
There is a possibility of using an rPi on an Ethernet cable to the PC
with direct comms to each test fixture board, but that's more work
that I'm interested in.
convenient.
But it's yet another piece to keep working. Much easier to just use the multi-drop. I will keep that idea as a backup plan. But getting RS-422 on an rPi is a hassle. That would need to be a hat, or a shield or whatever they call daughter cards on
If you are familiar with socat, the Pi doesn't necessarily need anyTo be fair, I don't recall any testbenches we've made that needed
more than perhaps 8 serial ports. If I needed to handle 80 lines, I
would probably split things up - a Pi handling 8-10 lines from a
local program, communicating with a PC master program by Ethernet.
That's the advantage of the shared bus. No programming required,
other than extending the protocol to move from "selecting" a device
on the FPGA, to selecting the FPGA as well.
programming either. (In our case we wanted some extra monitoring and
logging, which was more than we could get from socat - so it was a
couple of hundred lines of Python in the end.)
A couple hundred lines I'd rather not write.
Thanks for the comments.
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown wrote:
On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown
wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bit
(typically sub-slot 9 of 16). The first transmitter will be disabled at
the end of the stop bit, and the next transmitter must not enable its
driver until after that point - it must wait at least half a bit time
after reception before starting transmission. (It can wait longer
without trouble, which is why faster baud rates are less likely to
involve any complications here.)
None of this matters to me really. I'm going to use more wires, and
do the multi-drop from the PC to the slaves on one pair and use RS-422
to multi-point from the slaves to the PC. Since the slaves are
controlled by the master, they will never collide. The master can't
collide with itself, so I can ignore any issues with this. I will use
the bias resistors to assure a valid idle state. I may need to select
different devices than the ones I use in the product. I think there
are differences in the input load and I want to be sure I can chain up
to 32 units.
OK. I have no idea what such a hybrid bus should technically be called,
but I think it should work absolutely fine for the purpose and seems
like a solid solution. I would not foresee any issues with 32 nodes on
such a bus, especially if it is relatively short and you have
terminators at each end.
Il 03/11/2022 12:42, David Brown ha scritto:
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown wrote:
On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown
wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bit
(typically sub-slot 9 of 16). The first transmitter will be disabled
at the end of the stop bit, and the next transmitter must not enable
its driver until after that point - it must wait at least half a bit
time after reception before starting transmission. (It can wait
longer without trouble, which is why faster baud rates are less likely
to involve any complications here.)
Do you mean that RX interrupt triggers in the middle of the stop bit and
not at the end? Interesting, but are you sure this is the case for every
UART implemented in MCUs?
I wouldn't be surprised if the implementation was different for
different manufacturers.
None of this matters to me really. I'm going to use more wires, and
do the multi-drop from the PC to the slaves on one pair and use
RS-422 to multi-point from the slaves to the PC. Since the slaves
are controlled by the master, they will never collide. The master
can't collide with itself, so I can ignore any issues with this. I
will use the bias resistors to assure a valid idle state. I may need
to select different devices than the ones I use in the product. I
think there are differences in the input load and I want to be sure I
can chain up to 32 units.
OK. I have no idea what such a hybrid bus should technically be
called, but I think it should work absolutely fine for the purpose and
seems like a solid solution. I would not foresee any issues with 32
nodes on such a bus, especially if it is relatively short and you have
terminators at each end.
In my experience, termination resistors at each end of the line could introduce other troubles if they aren't strictly required (because of
signal integrity on long lines at high baud rates).
The receiver input impedance of all the nodes on the bus are in parallel
with the two terminators. If you have many nodes, the equivalent
impedance on the bus is much small and the partition with bias resistors could reduce the differential voltage between A and B at idle to less
than 200mV.
If you don't use true fail-safe transceivers, a fault start bit could be
seen by these kind of receivers.
Il 03/11/2022 12:42, David Brown ha scritto:
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown wrote: >>> On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown
wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bitDo you mean that RX interrupt triggers in the middle of the stop bit and
(typically sub-slot 9 of 16). The first transmitter will be disabled at the end of the stop bit, and the next transmitter must not enable its driver until after that point - it must wait at least half a bit time after reception before starting transmission. (It can wait longer
without trouble, which is why faster baud rates are less likely to
involve any complications here.)
not at the end? Interesting, but are you sure this is the case for every UART implemented in MCUs?
I wouldn't be surprised if the implementation was different for
different manufacturers.
None of this matters to me really. I'm going to use more wires, and
do the multi-drop from the PC to the slaves on one pair and use RS-422
to multi-point from the slaves to the PC. Since the slaves are
controlled by the master, they will never collide. The master can't
collide with itself, so I can ignore any issues with this. I will use
the bias resistors to assure a valid idle state. I may need to select
different devices than the ones I use in the product. I think there
are differences in the input load and I want to be sure I can chain up
to 32 units.
OK. I have no idea what such a hybrid bus should technically be called, but I think it should work absolutely fine for the purpose and seemsIn my experience, termination resistors at each end of the line could introduce other troubles if they aren't strictly required (because of
like a solid solution. I would not foresee any issues with 32 nodes on such a bus, especially if it is relatively short and you have
terminators at each end.
signal integrity on long lines at high baud rates).
The receiver input impedance of all the nodes on the bus are in parallel with the two terminators. If you have many nodes, the equivalent
impedance on the bus is much small and the partition with bias resistors could reduce the differential voltage between A and B at idle to less
than 200mV.
If you don't use true fail-safe transceivers, a fault start bit could be seen by these kind of receivers.
What hardware can you replace with software??? You use *different*
hardware and then have to add new software. That's not an
improvement.
I think my biggest problem is going to be the mechanical parts of the chassis. I need the boards to be very strong to withstand many
insertion removal cycles of the UUTs from these boards.
Rick C <[email protected]> writes:
What hardware can you replace with software??? You use *different* hardware and then have to add new software. That's not anThe idea is to avoid BUILDING hardware. Plugging cables into a box is
improvement.
not building. There is no soldering iron, oscilloscope, or anything
like that in the picture. If you already avoid that, then great.
Rick C <[email protected]> writes:
I think my biggest problem is going to be the mechanical parts of the chassis. I need the boards to be very strong to withstand manyI wonder if you can use some kind of low-force connector or cable on the card, instead of plugging and unplugging the card from a chassis.
insertion removal cycles of the UUTs from these boards.
E.g. something like https://www.adafruit.com/product/5468 depending on
how many conductors are needed.
I have a test fixture that uses RS-232 to communicate with a PC. It actually uses the voltage levels of RS-232, even though this is from a USB cable on the PC, so it's only RS-232 for maybe four inches. lolUUTs total. There will be an FPGA controlling each pair of UUTs, so 80 FPGAs in total that the PC needs to talk to.
I'm redesigning the test fixtures to hold more units and fully automate a few features that presently requires an operator. There will now be 8 UUTs on each test fixture and I expect to have 10 to 20 test fixtures in a card rack. That's 80 to 160
Rather than working on a way to mux 80 RS-232 interfaces, I'm thinking it would be better to either daisy chain, or connect in parallel all these devices. The protocol is master-slave where the master sends a command and the slaves are idle until theyreply. The four FPGAs on a test fixture board could be connected in parallel easily enough. But I don't think I want to run TTL level signals between so many boards.
I could do an RS-422 interface with a master to slave pair and a slave to master pair. The slaves do not speak until spoken to, so there will be no collisions.start bit by overwriting the stop bit of the slave. I suppose someone, somewhere has dealt with this on the PC and has a solution that doesn't impact bus speed. I run the single test fixture version of this at about 100 kbps. I'm going to want as much
RS-485 would allow all this to be over a single pair of wires. But the one big issue I see people complain about is getting PC software to not clobber the slaves, or I should say, to get the master to wait long enough that it's not clobbering it's own
The tests are of two types, most of them are setting up a state and reading a signal. This can go pretty fast and doesn't take too many commands. Then there are the audio tests where the FPGA sends digital data to the UUT, which does it's thing andreturns digital data which is crunched by the FPGA. This takes some small number of seconds and presently the protocol is to poll the status until it is done. That's a lot of messages, but it's not necessarily a slow point. The same test can be
Still, I want to use RS-422 or RS-485 to deal with ground noise since this will be spread over multiple boards that don't have terribly solid grounds, just the power cable really.side, allowing the transceivers to be used either way.
I'm thinking out loud here as much as anything. I intended to simply ask if anyone had experience with RS-485 that would be helpful. Running two wires rather than eight would be a help. I'll probably use a 10 pin connector just to be on the safe
How about something like this?
https://www.digikey.com/en/products/detail/amphenol-cs-commercial-products/RJHSE538B02/1979553
The bottom line is, you don't know much about the application, but
think you can design it better. Why are you doing this?
Rick C <[email protected]> writes:
The bottom line is, you don't know much about the application, butYou asked for suggestions and I gave some.
think you can design it better. Why are you doing this?
On 11/2/2022 1:28 AM, Rick C wrote:UUTs total. There will be an FPGA controlling each pair of UUTs, so 80 FPGAs in total that the PC needs to talk to.
I have a test fixture that uses RS-232 to communicate with a PC. It actually uses the voltage levels of RS-232, even though this is from a USB cable on the PC, so it's only RS-232 for maybe four inches. lol
I'm redesigning the test fixtures to hold more units and fully automate a few features that presently requires an operator. There will now be 8 UUTs on each test fixture and I expect to have 10 to 20 test fixtures in a card rack. That's 80 to 160
they reply. The four FPGAs on a test fixture board could be connected in parallel easily enough. But I don't think I want to run TTL level signals between so many boards.Rather than working on a way to mux 80 RS-232 interfaces, I'm thinking it would be better to either daisy chain, or connect in parallel all these devices. The protocol is master-slave where the master sends a command and the slaves are idle until
own start bit by overwriting the stop bit of the slave. I suppose someone, somewhere has dealt with this on the PC and has a solution that doesn't impact bus speed. I run the single test fixture version of this at about 100 kbps. I'm going to want asI could do an RS-422 interface with a master to slave pair and a slave to master pair. The slaves do not speak until spoken to, so there will be no collisions.
RS-485 would allow all this to be over a single pair of wires. But the one big issue I see people complain about is getting PC software to not clobber the slaves, or I should say, to get the master to wait long enough that it's not clobbering it's
returns digital data which is crunched by the FPGA. This takes some small number of seconds and presently the protocol is to poll the status until it is done. That's a lot of messages, but it's not necessarily a slow point. The same test can be startedThe tests are of two types, most of them are setting up a state and reading a signal. This can go pretty fast and doesn't take too many commands. Then there are the audio tests where the FPGA sends digital data to the UUT, which does it's thing and
allowing the transceivers to be used either way.Still, I want to use RS-422 or RS-485 to deal with ground noise since this will be spread over multiple boards that don't have terribly solid grounds, just the power cable really.
I'm thinking out loud here as much as anything. I intended to simply ask if anyone had experience with RS-485 that would be helpful. Running two wires rather than eight would be a help. I'll probably use a 10 pin connector just to be on the safe side,
Hi Rick - I have an RS-485 system on my desk using an implementation of
the old Intel BitBus. Works fine for a handful of nodes, limited
distance, and very simple cabling - but only 62.5kbaud. Good solid technology for 1994 when I designed it...
Why would you use RS-485 instead of CAN? A million chips out there
support CAN with no fuss, works at decent speeds over twisted pair, not
hard to use.
BTW, another option for interfacing to RS-485 from USB is XR21B1411
which is what I happen to have on my desk.
Rick C <[email protected]> writes:
How about something like this?
https://www.digikey.com/en/products/detail/amphenol-cs-commercial-products/RJHSE538B02/1979553That appears to be an RJ45 like ethernet cables use. The little locking
tabs break off all the time, and also the cable gets kinked up after repeated flexing where it goes into the connector. Strain relief helps
but it happens anyway. You might buy some ready made ethernet cables
rather than putting those connectors on yourself. At least with cheap crimpers, the ready made cables are often more reliable than DIY ones.
They do make those magnetic connectors with varying numbers of pins.
Here is a CAN cable, no idea if that is of interest, but it uses the
OBD connector found in cars: https://www.adafruit.com/product/4841
XLR or DIN style plugs/sockets might also be something to consider.
There is also this style, popular with the mechanical keyboard crowd: https://www.pchcables.com/aviationplugs.html
DIN? You mean those things that are used on Eurocards with some 96
pins?
What would mate with it? What's actually wrong with RJ-45?
Rick C <[email protected]> writes:
DIN? You mean those things that are used on Eurocards with some 96No I meant the circular connectors like you see on old PC keyboards,
pins?
similar to the aviation style one that I linked.
What would mate with it? What's actually wrong with RJ-45?1) the plugs break and the cables get munged up, but as you can say you
can replace them when they do.
2) the sockets also break, maybe not as often, but replacing them
might be harder, depending
If both of those are ok with you, then maybe it a good choice.
On 03/11/2022 14:00, pozz wrote:
Il 03/11/2022 12:42, David Brown ha scritto:
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown wrote: >>>>> On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown
wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bit
(typically sub-slot 9 of 16). The first transmitter will be disabled
at the end of the stop bit, and the next transmitter must not enable
its driver until after that point - it must wait at least half a bit
time after reception before starting transmission. (It can wait
longer without trouble, which is why faster baud rates are less
likely to involve any complications here.)
Do you mean that RX interrupt triggers in the middle of the stop bit
and not at the end? Interesting, but are you sure this is the case for
every UART implemented in MCUs?
Of course I'm not sure - there are a /lot/ of MCU manufacturers!
UART receivers usually work in the same way, however. They have a
sample clock running at 16 times the baud clock. The start bit is edge triggered to give the start of the character frame. Then each bit is sampled in the middle of its time slot - usually at subbit slots 7, 8,
and 9 with majority voting. So the stop bit is recognized by subbit
slot 9 of the tenth bit (assuming 8-bit, no parity) - the voltage on the
line after that is irrelevant. (Even when you have two stop bits,
receivers never check the second stop bit - it affects transmit timing only.) What purpose would there be in waiting another 7 subbits before triggering the interrupt, DMA, or whatever?
I wouldn't be surprised if the implementation was different for
different manufacturers.
I've seen a bit of variation, including 8 subbit clocks per baud clock,
wider sampling ranges, re-sync of the clock on edges, etc. And of
course you don't always get the details of the timings in datasheets
(and who bothers measuring them?) But the key principles are the same.
None of this matters to me really. I'm going to use more wires, and
do the multi-drop from the PC to the slaves on one pair and use
RS-422 to multi-point from the slaves to the PC. Since the slaves
are controlled by the master, they will never collide. The master
can't collide with itself, so I can ignore any issues with this. I
will use the bias resistors to assure a valid idle state. I may
need to select different devices than the ones I use in the
product. I think there are differences in the input load and I want
to be sure I can chain up to 32 units.
OK. I have no idea what such a hybrid bus should technically be
called, but I think it should work absolutely fine for the purpose
and seems like a solid solution. I would not foresee any issues with
32 nodes on such a bus, especially if it is relatively short and you
have terminators at each end.
In my experience, termination resistors at each end of the line could
introduce other troubles if they aren't strictly required (because of
signal integrity on long lines at high baud rates).
RS-485 requires them - you want to hold the bus at a stable idle state
when nothing is driving it.
You also want to have a bit of load so that
you have some current on the bus, and thereby greater noise immunity.
The receiver input impedance of all the nodes on the bus are in
parallel with the two terminators. If you have many nodes, the
equivalent impedance on the bus is much small and the partition with
bias resistors could reduce the differential voltage between A and B
at idle to less than 200mV.
If you don't use true fail-safe transceivers, a fault start bit could
be seen by these kind of receivers.
Receiver load is very small on modern RS-485 drivers.
Rick C <[email protected]> writes:
How about something like this?
https://www.digikey.com/en/products/detail/amphenol-cs-commercial-products/RJHSE538B02/1979553
That appears to be an RJ45 like ethernet cables use. The little locking
tabs break off all the time, and also the cable gets kinked up after
repeated flexing where it goes into the connector. Strain relief helps
but it happens anyway. You might buy some ready made ethernet cables
rather than putting those connectors on yourself. At least with cheap crimpers, the ready made cables are often more reliable than DIY ones.
Il 03/11/2022 16:26, David Brown ha scritto:
On 03/11/2022 14:00, pozz wrote:
Il 03/11/2022 12:42, David Brown ha scritto:
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown wrote: >>>>>> On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown
wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bit
(typically sub-slot 9 of 16). The first transmitter will be
disabled at the end of the stop bit, and the next transmitter must
not enable its driver until after that point - it must wait at least
half a bit time after reception before starting transmission. (It
can wait longer without trouble, which is why faster baud rates are
less likely to involve any complications here.)
Do you mean that RX interrupt triggers in the middle of the stop bit
and not at the end? Interesting, but are you sure this is the case
for every UART implemented in MCUs?
Of course I'm not sure - there are a /lot/ of MCU manufacturers!
UART receivers usually work in the same way, however. They have a
sample clock running at 16 times the baud clock. The start bit is
edge triggered to give the start of the character frame. Then each
bit is sampled in the middle of its time slot - usually at subbit
slots 7, 8, and 9 with majority voting. So the stop bit is recognized
by subbit slot 9 of the tenth bit (assuming 8-bit, no parity) - the
voltage on the line after that is irrelevant. (Even when you have two
stop bits, receivers never check the second stop bit - it affects
transmit timing only.) What purpose would there be in waiting another
7 subbits before triggering the interrupt, DMA, or whatever?
There's no real purpose, but it's important to know exactly when the RX interrupt is fired from the UART.
Usually the next transmitter starts transmitting after receiving the
last byte of the previous transmitter (for example, the slave starts
replying to the master after receiving the complete message from it).
Now I think of the issue related to a transmitter that delays a little
to turn around the direction of its transceiver, from TX to RX. Every transmitter on the bus should take into account this delay and avoid
starting transmission too soon.
So I usually implement a short delay before starting a new message transmission. If the maximum expected delay of moving the direction from
TX to RX is 10us, I could think to use a 10us delay, but this is wrong
in your assumption.
If the RX interrupt is at the middle of the stop bit, I should delay the
new transmission of 10us + half of bit time. With 9600 this is 52us that
is much higher than 10us.
I know the next transmitter should make some processing of the previous received message, prepare and buffer the new message to transmit, so the delay is somewhat automatic, but in many cases I have small 8-bits PICs
and full-futured Linux box on the same bus and the Linux could be very
fast to start the new transmission.
I wouldn't be surprised if the implementation was different for
different manufacturers.
I've seen a bit of variation, including 8 subbit clocks per baud
clock, wider sampling ranges, re-sync of the clock on edges, etc. And
of course you don't always get the details of the timings in
datasheets (and who bothers measuring them?) But the key principles
are the same.
None of this matters to me really. I'm going to use more wires,
and do the multi-drop from the PC to the slaves on one pair and use
RS-422 to multi-point from the slaves to the PC. Since the slaves
are controlled by the master, they will never collide. The master
can't collide with itself, so I can ignore any issues with this. I >>>>> will use the bias resistors to assure a valid idle state. I may
need to select different devices than the ones I use in the
product. I think there are differences in the input load and I
want to be sure I can chain up to 32 units.
OK. I have no idea what such a hybrid bus should technically be
called, but I think it should work absolutely fine for the purpose
and seems like a solid solution. I would not foresee any issues
with 32 nodes on such a bus, especially if it is relatively short
and you have terminators at each end.
In my experience, termination resistors at each end of the line could
introduce other troubles if they aren't strictly required (because of
signal integrity on long lines at high baud rates).
RS-485 requires them - you want to hold the bus at a stable idle state
when nothing is driving it.
But this is the goal of *bias* resistors, not termination resistors.
You also want to have a bit of load so that you have some current on
the bus, and thereby greater noise immunity.
Of course, but termination resistors are usually small (around 100 ohms) because they should match the impedance of the cable. If you want only
to introduce "some current" on the bus, you could use resistors in the
order of 1k, but this isn't strictly a *termination* resistor.
The receiver input impedance of all the nodes on the bus are in
parallel with the two terminators. If you have many nodes, the
equivalent impedance on the bus is much small and the partition with
bias resistors could reduce the differential voltage between A and B
at idle to less than 200mV.
If you don't use true fail-safe transceivers, a fault start bit could
be seen by these kind of receivers.
Receiver load is very small on modern RS-485 drivers.
ST3485 says the input load of the receiver around 24k. When you connect
32 slaves, the equivalent resistor would be 750 ohms, that should be
enough to have "some current" on the bus. If you add *termination*
resistors in the order of 100R on both sides, you could reduce
drastically the differential voltage between A and B at idle state.
Yeah, I'm fine with a cable I can make to any length I want in 5 minutes, with most of that spent finding where I put the parts and tool. Oh, and costs less than $1.
On 04/11/2022 08:45, pozz wrote:
Il 03/11/2022 16:26, David Brown ha scritto:
On 03/11/2022 14:00, pozz wrote:
Il 03/11/2022 12:42, David Brown ha scritto:
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown
wrote:
On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown >>>>>>>> wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bitDo you mean that RX interrupt triggers in the middle of the stop bit
(typically sub-slot 9 of 16). The first transmitter will be
disabled at the end of the stop bit, and the next transmitter must
not enable its driver until after that point - it must wait at
least half a bit time after reception before starting
transmission. (It can wait longer without trouble, which is why
faster baud rates are less likely to involve any complications here.) >>>>
and not at the end? Interesting, but are you sure this is the case
for every UART implemented in MCUs?
Of course I'm not sure - there are a /lot/ of MCU manufacturers!
UART receivers usually work in the same way, however. They have a
sample clock running at 16 times the baud clock. The start bit is
edge triggered to give the start of the character frame. Then each
bit is sampled in the middle of its time slot - usually at subbit
slots 7, 8, and 9 with majority voting. So the stop bit is
recognized by subbit slot 9 of the tenth bit (assuming 8-bit, no
parity) - the voltage on the line after that is irrelevant. (Even
when you have two stop bits, receivers never check the second stop
bit - it affects transmit timing only.) What purpose would there be
in waiting another 7 subbits before triggering the interrupt, DMA, or
whatever?
There's no real purpose, but it's important to know exactly when the
RX interrupt is fired from the UART.
I think it is extremely rare that this is important. I can't think of a single occasion when I have thought it remotely relevant where in the
stop bit the interrupt comes.
Usually the next transmitter starts transmitting after receiving the
last byte of the previous transmitter (for example, the slave starts
replying to the master after receiving the complete message from it).
No. Usually the next transmitter starts after receiving the last byte,
and /then a pause/. There will always be some handling time in
software, and may also include an explicit pause. Almost always you
will want to do at least a minimum of checking of the incoming data
before deciding on the next telegram to be sent out. But if you have
very fast handling in relation to the baud rate, you will want an
explicit pause too - protocols regularly specify a minimum pause (such
as 3.5 character times for Modbus RTU), and you definitely want it to be
at least one full character time to ensure no listener gets hopelessly
out of sync.
Now I think of the issue related to a transmitter that delays a little
to turn around the direction of its transceiver, from TX to RX. Every
transmitter on the bus should take into account this delay and avoid
starting transmission too soon.
They should, yes. The turnaround delay should be negligible in this day
and age - if not, your software design is screwed or you have picked the wrong hardware. (Of course, you don't always get the choice of hardware
you want, and programmers are often left to find ways around hardware
design flaws.)
So I usually implement a short delay before starting a new message
transmission. If the maximum expected delay of moving the direction
from TX to RX is 10us, I could think to use a 10us delay, but this is
wrong in your assumption.
Implementing an explicit delay (or being confident that your telegram handling code takes long enough) is a good idea.
If the RX interrupt is at the middle of the stop bit, I should delay
the new transmission of 10us + half of bit time. With 9600 this is
52us that is much higher than 10us.
I made no such assumptions about timings. The figures I gave were for
using a USB 2 based interface on a PC, where the USB polling timer is at
8 kHz, or 125 µs. That is half a bit time for 4 Kbaud. (I had doubled the frequency instead of halving it and said the baud had to be above 16 kBaud - that shows it's good to do your own calculations and not trust
others blindly!). At 1 MBaud (the suggested rate), the absolute fastest
the PC could turn around the bus would be 12 character times - half a
stop bit is irrelevant.
If you have a 9600 baud RS-485 receiver and you have a delay of 10 µs between reception of the last bit and the start of transmission of the
next message, your code is wrong - by nearly two orders of magnitude. It
is that simple.
If we take Modbus RTU as an example, you should be waiting 3.5 * 10 /
9600 seconds at a minimum - 3.65 /milli/seconds. If you are concerned
about exactly where the receive interrupt comes in the last stop bit,
add another half bit time and you get 3.7 ms. The half bit time is negligible.
I know the next transmitter should make some processing of the
previous received message, prepare and buffer the new message to
transmit, so the delay is somewhat automatic, but in many cases I have
small 8-bits PICs and full-futured Linux box on the same bus and the
Linux could be very fast to start the new transmission.
So put in a delay. An /appropriate/ delay.
I wouldn't be surprised if the implementation was different for
different manufacturers.
I've seen a bit of variation, including 8 subbit clocks per baud
clock, wider sampling ranges, re-sync of the clock on edges, etc.
And of course you don't always get the details of the timings in
datasheets (and who bothers measuring them?) But the key principles
are the same.
None of this matters to me really. I'm going to use more wires,
and do the multi-drop from the PC to the slaves on one pair and
use RS-422 to multi-point from the slaves to the PC. Since the
slaves are controlled by the master, they will never collide. The >>>>>> master can't collide with itself, so I can ignore any issues with
this. I will use the bias resistors to assure a valid idle
state. I may need to select different devices than the ones I use >>>>>> in the product. I think there are differences in the input load
and I want to be sure I can chain up to 32 units.
OK. I have no idea what such a hybrid bus should technically be
called, but I think it should work absolutely fine for the purpose
and seems like a solid solution. I would not foresee any issues
with 32 nodes on such a bus, especially if it is relatively short
and you have terminators at each end.
In my experience, termination resistors at each end of the line
could introduce other troubles if they aren't strictly required
(because of signal integrity on long lines at high baud rates).
RS-485 requires them - you want to hold the bus at a stable idle
state when nothing is driving it.
But this is the goal of *bias* resistors, not termination resistors.
Yes - but see below. Bias resistors are part of the termination - it
just means that you have terminating resistors to 5V and 0V as well as
across the balanced pair.
You also want to have a bit of load so that you have some current on
the bus, and thereby greater noise immunity.
Of course, but termination resistors are usually small (around 100
ohms) because they should match the impedance of the cable. If you
want only to introduce "some current" on the bus, you could use
resistors in the order of 1k, but this isn't strictly a *termination*
resistor.
If you have a cable that is long enough (or speeds fast enough) that it
needs to be treated as a transmission line with controlled impedance,
then you do need impedance matched terminators to avoid reflections
causing trouble. Usually you don't.
A "terminating resistor" is just a "resistor at the terminator" - it
does not imply impedance matching, or any other specific purpose. You
pick a value (and network) appropriate for the task in hand - maybe you impedance matching, maybe you'd rather have larger values to reduce
power consumption.
The receiver input impedance of all the nodes on the bus are in
parallel with the two terminators. If you have many nodes, the
equivalent impedance on the bus is much small and the partition with
bias resistors could reduce the differential voltage between A and B
at idle to less than 200mV.
If you don't use true fail-safe transceivers, a fault start bit
could be seen by these kind of receivers.
Receiver load is very small on modern RS-485 drivers.
ST3485 says the input load of the receiver around 24k. When you
connect 32 slaves, the equivalent resistor would be 750 ohms, that
should be enough to have "some current" on the bus. If you add
*termination* resistors in the order of 100R on both sides, you could
reduce drastically the differential voltage between A and B at idle
state.
If you are pushing the limits of a bus, in terms of load, distance,
speed, cable characteristics, etc., then you need to do such
calculations carefully and be precise in your specification of
components, cables, topology, connectors, etc. For many buses in
practice, they will work fine using whatever resistor you pull out your
box of random parts. For a testbench, you are going to go for something between these extremes.
On 04/11/2022 08:45, pozz wrote:
Il 03/11/2022 16:26, David Brown ha scritto:
On 03/11/2022 14:00, pozz wrote:
Il 03/11/2022 12:42, David Brown ha scritto:
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown wrote: >>>>>> On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown >>>>>>> wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bit
(typically sub-slot 9 of 16). The first transmitter will be
disabled at the end of the stop bit, and the next transmitter must
not enable its driver until after that point - it must wait at least >>>> half a bit time after reception before starting transmission. (It
can wait longer without trouble, which is why faster baud rates are >>>> less likely to involve any complications here.)
Do you mean that RX interrupt triggers in the middle of the stop bit
and not at the end? Interesting, but are you sure this is the case
for every UART implemented in MCUs?
Of course I'm not sure - there are a /lot/ of MCU manufacturers!
UART receivers usually work in the same way, however. They have a
sample clock running at 16 times the baud clock. The start bit is
edge triggered to give the start of the character frame. Then each
bit is sampled in the middle of its time slot - usually at subbit
slots 7, 8, and 9 with majority voting. So the stop bit is recognized
by subbit slot 9 of the tenth bit (assuming 8-bit, no parity) - the
voltage on the line after that is irrelevant. (Even when you have two
stop bits, receivers never check the second stop bit - it affects
transmit timing only.) What purpose would there be in waiting another
7 subbits before triggering the interrupt, DMA, or whatever?
There's no real purpose, but it's important to know exactly when the RX interrupt is fired from the UART.
I think it is extremely rare that this is important. I can't think of a single occasion when I have thought it remotely relevant where in the
stop bit the interrupt comes.
Usually the next transmitter starts transmitting after receiving the
last byte of the previous transmitter (for example, the slave starts replying to the master after receiving the complete message from it).
No. Usually the next transmitter starts after receiving the last byte,
and /then a pause/. There will always be some handling time in
software, and may also include an explicit pause. Almost always you
will want to do at least a minimum of checking of the incoming data
before deciding on the next telegram to be sent out. But if you have
very fast handling in relation to the baud rate, you will want an
explicit pause too - protocols regularly specify a minimum pause (such
as 3.5 character times for Modbus RTU), and you definitely want it to be
at least one full character time to ensure no listener gets hopelessly
out of sync.
Now I think of the issue related to a transmitter that delays a littleThey should, yes. The turnaround delay should be negligible in this day
to turn around the direction of its transceiver, from TX to RX. Every transmitter on the bus should take into account this delay and avoid starting transmission too soon.
and age - if not, your software design is screwed or you have picked the wrong hardware. (Of course, you don't always get the choice of hardware
you want, and programmers are often left to find ways around hardware
design flaws.)
So I usually implement a short delay before starting a new message transmission. If the maximum expected delay of moving the direction from TX to RX is 10us, I could think to use a 10us delay, but this is wrong
in your assumption.
Implementing an explicit delay (or being confident that your telegram handling code takes long enough) is a good idea.
If the RX interrupt is at the middle of the stop bit, I should delay the new transmission of 10us + half of bit time. With 9600 this is 52us that is much higher than 10us.
I made no such assumptions about timings. The figures I gave were for
using a USB 2 based interface on a PC, where the USB polling timer is at
8 kHz, or 125 µs. That is half a bit time for 4 Kbaud. (I had doubled
the frequency instead of halving it and said the baud had to be above 16 kBaud - that shows it's good to do your own calculations and not trust others blindly!). At 1 MBaud (the suggested rate), the absolute fastest
the PC could turn around the bus would be 12 character times - half a
stop bit is irrelevant.
If you have a 9600 baud RS-485 receiver and you have a delay of 10 µs between reception of the last bit and the start of transmission of the
next message, your code is wrong - by nearly two orders of magnitude.
It is that simple.
If we take Modbus RTU as an example, you should be waiting 3.5 * 10 /
9600 seconds at a minimum - 3.65 /milli/seconds. If you are concerned
about exactly where the receive interrupt comes in the last stop bit,
add another half bit time and you get 3.7 ms. The half bit time is negligible.
I know the next transmitter should make some processing of the previous received message, prepare and buffer the new message to transmit, so the delay is somewhat automatic, but in many cases I have small 8-bits PICs and full-futured Linux box on the same bus and the Linux could be very fast to start the new transmission.
So put in a delay. An /appropriate/ delay.
I wouldn't be surprised if the implementation was different for
different manufacturers.
I've seen a bit of variation, including 8 subbit clocks per baud
clock, wider sampling ranges, re-sync of the clock on edges, etc. And
of course you don't always get the details of the timings in
datasheets (and who bothers measuring them?) But the key principles
are the same.
None of this matters to me really. I'm going to use more wires,
and do the multi-drop from the PC to the slaves on one pair and use >>>>> RS-422 to multi-point from the slaves to the PC. Since the slaves >>>>> are controlled by the master, they will never collide. The master >>>>> can't collide with itself, so I can ignore any issues with this. I >>>>> will use the bias resistors to assure a valid idle state. I may
need to select different devices than the ones I use in the
product. I think there are differences in the input load and I
want to be sure I can chain up to 32 units.
OK. I have no idea what such a hybrid bus should technically be
called, but I think it should work absolutely fine for the purpose
and seems like a solid solution. I would not foresee any issues
with 32 nodes on such a bus, especially if it is relatively short
and you have terminators at each end.
In my experience, termination resistors at each end of the line could >>> introduce other troubles if they aren't strictly required (because of >>> signal integrity on long lines at high baud rates).
RS-485 requires them - you want to hold the bus at a stable idle state
when nothing is driving it.
But this is the goal of *bias* resistors, not termination resistors.
Yes - but see below. Bias resistors are part of the termination - it
just means that you have terminating resistors to 5V and 0V as well as across the balanced pair.
You also want to have a bit of load so that you have some current on
the bus, and thereby greater noise immunity.
Of course, but termination resistors are usually small (around 100 ohms) because they should match the impedance of the cable. If you want only
to introduce "some current" on the bus, you could use resistors in the order of 1k, but this isn't strictly a *termination* resistor.
If you have a cable that is long enough (or speeds fast enough) that it needs to be treated as a transmission line with controlled impedance,
then you do need impedance matched terminators to avoid reflections
causing trouble. Usually you don't.
A "terminating resistor" is just a "resistor at the terminator" - it
does not imply impedance matching, or any other specific purpose. You
pick a value (and network) appropriate for the task in hand - maybe you impedance matching, maybe you'd rather have larger values to reduce
power consumption.
The receiver input impedance of all the nodes on the bus are in
parallel with the two terminators. If you have many nodes, the
equivalent impedance on the bus is much small and the partition with
bias resistors could reduce the differential voltage between A and B
at idle to less than 200mV.
If you don't use true fail-safe transceivers, a fault start bit could >>> be seen by these kind of receivers.
Receiver load is very small on modern RS-485 drivers.
ST3485 says the input load of the receiver around 24k. When you connect
32 slaves, the equivalent resistor would be 750 ohms, that should be enough to have "some current" on the bus. If you add *termination* resistors in the order of 100R on both sides, you could reduce
drastically the differential voltage between A and B at idle state.
If you are pushing the limits of a bus, in terms of load, distance,
speed, cable characteristics, etc., then you need to do such
calculations carefully and be precise in your specification of
components, cables, topology, connectors, etc. For many buses in
practice, they will work fine using whatever resistor you pull out your
box of random parts. For a testbench, you are going to go for something between these extremes.
On 04/11/2022 05:10, Rick C wrote:
Yeah, I'm fine with a cable I can make to any length I want in 5 minutes, with most of that spent finding where I put the parts and tool. Oh, and costs less than $1.
A cable you can make in 5 minutes doesn't cost $1, unless you earn less
than a hamburger flipper and the parts are free. The cost of a poor connection when making the cable could be huge in downtime of the
testbench. It should not be hard to get a bag of pre-made short
Ethernet cables for a couple of dollars per cable - it's probably
cheaper to buy an effectively unlimited supply than to buy a good
quality crimping tool.
Il 04/11/2022 10:49, David Brown ha scritto:
On 04/11/2022 08:45, pozz wrote:
Il 03/11/2022 16:26, David Brown ha scritto:
On 03/11/2022 14:00, pozz wrote:
Il 03/11/2022 12:42, David Brown ha scritto:
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown
wrote:
On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown >>>>>>>>> wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bitDo you mean that RX interrupt triggers in the middle of the stop
(typically sub-slot 9 of 16). The first transmitter will be
disabled at the end of the stop bit, and the next transmitter must >>>>>> not enable its driver until after that point - it must wait at
least half a bit time after reception before starting
transmission. (It can wait longer without trouble, which is why
faster baud rates are less likely to involve any complications here.) >>>>>
bit and not at the end? Interesting, but are you sure this is the
case for every UART implemented in MCUs?
Of course I'm not sure - there are a /lot/ of MCU manufacturers!
UART receivers usually work in the same way, however. They have a
sample clock running at 16 times the baud clock. The start bit is
edge triggered to give the start of the character frame. Then each
bit is sampled in the middle of its time slot - usually at subbit
slots 7, 8, and 9 with majority voting. So the stop bit is
recognized by subbit slot 9 of the tenth bit (assuming 8-bit, no
parity) - the voltage on the line after that is irrelevant. (Even
when you have two stop bits, receivers never check the second stop
bit - it affects transmit timing only.) What purpose would there be
in waiting another 7 subbits before triggering the interrupt, DMA,
or whatever?
There's no real purpose, but it's important to know exactly when the
RX interrupt is fired from the UART.
I think it is extremely rare that this is important. I can't think of
a single occasion when I have thought it remotely relevant where in
the stop bit the interrupt comes.
Usually the next transmitter starts transmitting after receiving the
last byte of the previous transmitter (for example, the slave starts
replying to the master after receiving the complete message from it).
No. Usually the next transmitter starts after receiving the last
byte, and /then a pause/. There will always be some handling time in
software, and may also include an explicit pause. Almost always you
will want to do at least a minimum of checking of the incoming data
before deciding on the next telegram to be sent out. But if you have
very fast handling in relation to the baud rate, you will want an
explicit pause too - protocols regularly specify a minimum pause (such
as 3.5 character times for Modbus RTU), and you definitely want it to
be at least one full character time to ensure no listener gets
hopelessly out of sync.
In theory, if all the nodes on the bus were able to change direction in hardware (exactly at the end of the stop bit), you will not be forced to introduce any delay in the transmission.
Many times I'm the author of a custom protocol because some nodes on a
shared bus, so I'm not forced to follow any specifications. When I
didn't introduce any delay in the transmission, I sometimes faced this
issue. In my experience, the bus is heterogeneous enough to have a fast replying slave to a slow master.
Now I think of the issue related to a transmitter that delays a
little to turn around the direction of its transceiver, from TX to
RX. Every transmitter on the bus should take into account this delay
and avoid starting transmission too soon.
They should, yes. The turnaround delay should be negligible in this
day and age - if not, your software design is screwed or you have
picked the wrong hardware. (Of course, you don't always get the
choice of hardware you want, and programmers are often left to find
ways around hardware design flaws.)
Negligible doesn't mean anything.
If thre's a poor 8 bit PIC (previous
transmitter) clocked at 8MHz that changes direction in TXC interrupt
while other interrupts are active, and there's a Cortex-M4 clocked at
200MHz (next transmitter), you will encounter this issue.
This is more evident if, as you are saying, the Cortex-M4 is able to
start processing the message from the PIC at the midpoint of last stop
bit, while the PIC disables its driver at the *end* of the stop bit plus
an additional delay caused by interrupts handling.
In this cases the half bit time is not negligible and must be added to
the transmission delay.
So I usually implement a short delay before starting a new message
transmission. If the maximum expected delay of moving the direction
from TX to RX is 10us, I could think to use a 10us delay, but this is
wrong in your assumption.
Implementing an explicit delay (or being confident that your telegram
handling code takes long enough) is a good idea.
If the RX interrupt is at the middle of the stop bit, I should delay
the new transmission of 10us + half of bit time. With 9600 this is
52us that is much higher than 10us.
I made no such assumptions about timings. The figures I gave were for
using a USB 2 based interface on a PC, where the USB polling timer is
at 8 kHz, or 125 µs. That is half a bit time for 4 Kbaud. (I had
doubled the frequency instead of halving it and said the baud had to
be above 16 kBaud - that shows it's good to do your own calculations
and not trust others blindly!). At 1 MBaud (the suggested rate), the
absolute fastest the PC could turn around the bus would be 12
character times - half a stop bit is irrelevant.
If you have a 9600 baud RS-485 receiver and you have a delay of 10 µs
between reception of the last bit and the start of transmission of the
next message, your code is wrong - by nearly two orders of magnitude.
It is that simple.
Not always. If you have only MCUs that are able to control direction in hardware, you don't need any delay before transmission.
If we take Modbus RTU as an example, you should be waiting 3.5 * 10 /
9600 seconds at a minimum - 3.65 /milli/seconds. If you are concerned
about exactly where the receive interrupt comes in the last stop bit,
add another half bit time and you get 3.7 ms. The half bit time is
negligible.
Oh yes, if you have already implemented a pause of 3.5 char times, it is
ok.
I know the next transmitter should make some processing of the
previous received message, prepare and buffer the new message to
transmit, so the delay is somewhat automatic, but in many cases I
have small 8-bits PICs and full-futured Linux box on the same bus and
the Linux could be very fast to start the new transmission.
So put in a delay. An /appropriate/ delay.
I wouldn't be surprised if the implementation was different for
different manufacturers.
I've seen a bit of variation, including 8 subbit clocks per baud
clock, wider sampling ranges, re-sync of the clock on edges, etc.
And of course you don't always get the details of the timings in
datasheets (and who bothers measuring them?) But the key principles
are the same.
None of this matters to me really. I'm going to use more wires, >>>>>>> and do the multi-drop from the PC to the slaves on one pair and
use RS-422 to multi-point from the slaves to the PC. Since the >>>>>>> slaves are controlled by the master, they will never collide.
The master can't collide with itself, so I can ignore any issues >>>>>>> with this. I will use the bias resistors to assure a valid idle >>>>>>> state. I may need to select different devices than the ones I
use in the product. I think there are differences in the input >>>>>>> load and I want to be sure I can chain up to 32 units.
OK. I have no idea what such a hybrid bus should technically be
called, but I think it should work absolutely fine for the purpose >>>>>> and seems like a solid solution. I would not foresee any issues
with 32 nodes on such a bus, especially if it is relatively short
and you have terminators at each end.
In my experience, termination resistors at each end of the line
could introduce other troubles if they aren't strictly required
(because of signal integrity on long lines at high baud rates).
RS-485 requires them - you want to hold the bus at a stable idle
state when nothing is driving it.
But this is the goal of *bias* resistors, not termination resistors.
Yes - but see below. Bias resistors are part of the termination - it
just means that you have terminating resistors to 5V and 0V as well as
across the balanced pair.
You also want to have a bit of load so that you have some current on
the bus, and thereby greater noise immunity.
Of course, but termination resistors are usually small (around 100
ohms) because they should match the impedance of the cable. If you
want only to introduce "some current" on the bus, you could use
resistors in the order of 1k, but this isn't strictly a *termination*
resistor.
If you have a cable that is long enough (or speeds fast enough) that
it needs to be treated as a transmission line with controlled
impedance, then you do need impedance matched terminators to avoid
reflections causing trouble. Usually you don't.
A "terminating resistor" is just a "resistor at the terminator" - it
does not imply impedance matching, or any other specific purpose. You
pick a value (and network) appropriate for the task in hand - maybe
you impedance matching, maybe you'd rather have larger values to
reduce power consumption.
The receiver input impedance of all the nodes on the bus are in
parallel with the two terminators. If you have many nodes, the
equivalent impedance on the bus is much small and the partition
with bias resistors could reduce the differential voltage between A
and B at idle to less than 200mV.
If you don't use true fail-safe transceivers, a fault start bit
could be seen by these kind of receivers.
Receiver load is very small on modern RS-485 drivers.
ST3485 says the input load of the receiver around 24k. When you
connect 32 slaves, the equivalent resistor would be 750 ohms, that
should be enough to have "some current" on the bus. If you add
*termination* resistors in the order of 100R on both sides, you could
reduce drastically the differential voltage between A and B at idle
state.
If you are pushing the limits of a bus, in terms of load, distance,
speed, cable characteristics, etc., then you need to do such
calculations carefully and be precise in your specification of
components, cables, topology, connectors, etc. For many buses in
practice, they will work fine using whatever resistor you pull out
your box of random parts. For a testbench, you are going to go for
something between these extremes.
Ok, I thought you were suggesting to add impedance matching (slow)
resistors as terminators in any case.
On 04/11/2022 15:37, pozz wrote:
Il 04/11/2022 10:49, David Brown ha scritto:
On 04/11/2022 08:45, pozz wrote:
Il 03/11/2022 16:26, David Brown ha scritto:
On 03/11/2022 14:00, pozz wrote:
Il 03/11/2022 12:42, David Brown ha scritto:
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown >>>>>>> wrote:
On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown >>>>>>>>> wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bit >>>>>> (typically sub-slot 9 of 16). The first transmitter will beDo you mean that RX interrupt triggers in the middle of the stop
disabled at the end of the stop bit, and the next transmitter must >>>>>> not enable its driver until after that point - it must wait at
least half a bit time after reception before starting
transmission. (It can wait longer without trouble, which is why >>>>>> faster baud rates are less likely to involve any complications here.) >>>>>
bit and not at the end? Interesting, but are you sure this is the >>>>> case for every UART implemented in MCUs?
Of course I'm not sure - there are a /lot/ of MCU manufacturers!
UART receivers usually work in the same way, however. They have a
sample clock running at 16 times the baud clock. The start bit is
edge triggered to give the start of the character frame. Then each >>>> bit is sampled in the middle of its time slot - usually at subbit
slots 7, 8, and 9 with majority voting. So the stop bit is
recognized by subbit slot 9 of the tenth bit (assuming 8-bit, no
parity) - the voltage on the line after that is irrelevant. (Even
when you have two stop bits, receivers never check the second stop
bit - it affects transmit timing only.) What purpose would there be >>>> in waiting another 7 subbits before triggering the interrupt, DMA,
or whatever?
There's no real purpose, but it's important to know exactly when the
RX interrupt is fired from the UART.
I think it is extremely rare that this is important. I can't think of
a single occasion when I have thought it remotely relevant where in
the stop bit the interrupt comes.
Usually the next transmitter starts transmitting after receiving the
last byte of the previous transmitter (for example, the slave starts
replying to the master after receiving the complete message from it). >>>
No. Usually the next transmitter starts after receiving the last
byte, and /then a pause/. There will always be some handling time in
software, and may also include an explicit pause. Almost always you
will want to do at least a minimum of checking of the incoming data
before deciding on the next telegram to be sent out. But if you have
very fast handling in relation to the baud rate, you will want an
explicit pause too - protocols regularly specify a minimum pause (such
as 3.5 character times for Modbus RTU), and you definitely want it to
be at least one full character time to ensure no listener gets
hopelessly out of sync.
In theory, if all the nodes on the bus were able to change direction in hardware (exactly at the end of the stop bit), you will not be forced to introduce any delay in the transmission.Communication is about /reliably/ transferring data between devices. Asynchronous serial communication is about doing that despite slight differences in clock rates, differences in synchronisation, differences
in startup times, etc. If you don't have idle pauses, you have almost
zero chance of staying in sync across the nodes - and no chance at all
of recovery when that happens. /Every/ successful serial protocol has
pauses between frames - long enough pauses that the idle time could not possibly be part of a normal full speed frame. That does not just apply
to UART protocols, or even just to asynchronous protocols. The pause
does not have to be as long as 3.5 characters, but you need a pause -
just as you need other error recovery handling.
Many times I'm the author of a custom protocol because some nodes on a shared bus, so I'm not forced to follow any specifications. When I
didn't introduce any delay in the transmission, I sometimes faced this issue. In my experience, the bus is heterogeneous enough to have a fast replying slave to a slow master.
Now I think of the issue related to a transmitter that delays a
little to turn around the direction of its transceiver, from TX to
RX. Every transmitter on the bus should take into account this delay
and avoid starting transmission too soon.
They should, yes. The turnaround delay should be negligible in this
day and age - if not, your software design is screwed or you have
picked the wrong hardware. (Of course, you don't always get the
choice of hardware you want, and programmers are often left to find
ways around hardware design flaws.)
Negligible doesn't mean anything.Negligible means of no significance in comparison to the delays you have anyway - either intentional delays in order to separate telegrams and
have a reliable communication, or unavoidable delays due to software processing.
If thre's a poor 8 bit PIC (previous
transmitter) clocked at 8MHz that changes direction in TXC interrupt
while other interrupts are active, and there's a Cortex-M4 clocked at 200MHz (next transmitter), you will encounter this issue.
No, you won't - not unless you are doing something silly in your timing
such as failing to use appropriate pauses or thinking that 10 µs turnarounds are a good idea at 9600 baud. And I did specify picking
sensible hardware - 8-bit PICs were are terrible choice 20 years ago for anything involving high speed, and they have not improved. (Again - sometimes you don't have control of the hardware, and sometimes there
can be other overriding reasons for picking something. But if your
hardware is limited, you have to take that into account.)
This is more evident if, as you are saying, the Cortex-M4 is able to
start processing the message from the PIC at the midpoint of last stop bit, while the PIC disables its driver at the *end* of the stop bit plus an additional delay caused by interrupts handling.
In this cases the half bit time is not negligible and must be added to
the transmission delay.
Sorry, but I cannot see any situation where that would happen in a well-designed communication system.
Oh, and it is actually essential that the receiver considers the
character finished half-way through the stop bit, and not at the end.
UART communication is intended to work despite small differences in the
baud rate - up to nearly 5% total error. By the time the receiver is
half way through the received stop bit, and has identified it is valid,
the sender could be finished the stop bit as its clock is almost 5%
faster (50% bit time over the full 10 bits). The receiver has to be in
the "watch for falling edge of start bit" state at this point, ready for
the transmitter to start its next frame.
How long is a piece of string? By keeping the interconnecting cables short, 4" or so, and a 5 foot cable from the PC, I don't expect problems with reflections. But it is prudent to allow for them anyway. The FTDI RS-422 cable seems to have aterminator on the receiver, but not the driver and no provision to add a terminator to the driver.
Oddly enough, the RS-485 cable has a terminator that can be connected by the user, but that would be running through the cable separately from the transceiver signals, so essentially stubbed! I guess at 1 Mbps, 5 feet is less than the rise time, sonot an issue. Since the interconnections between cards will be about five feet as well, it's unlikely to be an issue. The entire network will look like a lumped load, with the propagation time on the order of the rise/fall time. Even adding in a
They sell cables that have 5 m of cable, with a round trip of 30 ns or so.
I think that would still not be significant in this application. The driver rise/fall times are 15 ns typ, 25 ns max.
I have a test fixture that uses RS-232 to communicate with a PC. It actually uses the voltage levels of RS-232, even though this is from a USB cable on the PC, so it's only RS-232 for maybe four inches. lolUUTs total. There will be an FPGA controlling each pair of UUTs, so 80 FPGAs in total that the PC needs to talk to.
I'm redesigning the test fixtures to hold more units and fully automate a few features that presently requires an operator. There will now be 8 UUTs on each test fixture and I expect to have 10 to 20 test fixtures in a card rack. That's 80 to 160
Rather than working on a way to mux 80 RS-232 interfaces, I'm thinking it would be better to either daisy chain, or connect in parallel all these devices. The protocol is master-slave where the master sends a command and the slaves are idle until theyreply. The four FPGAs on a test fixture board could be connected in parallel easily enough. But I don't think I want to run TTL level signals between so many boards.
I could do an RS-422 interface with a master to slave pair and a slave to master pair. The slaves do not speak until spoken to, so there will be no collisions.start bit by overwriting the stop bit of the slave. I suppose someone, somewhere has dealt with this on the PC and has a solution that doesn't impact bus speed. I run the single test fixture version of this at about 100 kbps. I'm going to want as much
RS-485 would allow all this to be over a single pair of wires. But the one big issue I see people complain about is getting PC software to not clobber the slaves, or I should say, to get the master to wait long enough that it's not clobbering it's own
The tests are of two types, most of them are setting up a state and reading a signal. This can go pretty fast and doesn't take too many commands. Then there are the audio tests where the FPGA sends digital data to the UUT, which does it's thing andreturns digital data which is crunched by the FPGA. This takes some small number of seconds and presently the protocol is to poll the status until it is done. That's a lot of messages, but it's not necessarily a slow point. The same test can be
Still, I want to use RS-422 or RS-485 to deal with ground noise since this will be spread over multiple boards that don't have terribly solid grounds, just the power cable really.side, allowing the transceivers to be used either way.
I'm thinking out loud here as much as anything. I intended to simply ask if anyone had experience with RS-485 that would be helpful. Running two wires rather than eight would be a help. I'll probably use a 10 pin connector just to be on the safe
Rick C <[email protected]> wrote:terminator on the receiver, but not the driver and no provision to add a terminator to the driver.
How long is a piece of string? By keeping the interconnecting cables short, 4" or so, and a 5 foot cable from the PC, I don't expect problems with reflections. But it is prudent to allow for them anyway. The FTDI RS-422 cable seems to have a
It is pointless to add terminator to driver, there will be mismatch
anyway and resistor would just waste transmit power. Mismatch
at driver does not case trouble as long as ends are properly
terminated. And when driver is at the near end and there are no
other drivers, then it is enough to put termination only at the
far end. So FTDI cable seem to be doing exactly what is needed.
not an issue. Since the interconnections between cards will be about five feet as well, it's unlikely to be an issue. The entire network will look like a lumped load, with the propagation time on the order of the rise/fall time. Even adding in a secondOddly enough, the RS-485 cable has a terminator that can be connected by the user, but that would be running through the cable separately from the transceiver signals, so essentially stubbed! I guess at 1 Mbps, 5 feet is less than the rise time, so
They sell cables that have 5 m of cable, with a round trip of 30 ns or so.Closer to 50 ns due to lower speed in cable.
I think that would still not be significant in this application. The driver rise/fall times are 15 ns typ, 25 ns max.Termination is also to kill _multiple_ reflections. In low loss line
you can have bunch of reflection creating jitter. When jitter is
more than 10% of bit time serial communication tends to have significant number of errors. At 9600 or at 100000 bits/s with short line bit
time is long enough that jitter due to reflections in untermined
line does not matter. Also multidrop RS-485 is far from low loss,
each extra drop weakens signal, so reflections die faster than
in quality point-to-point line.
On Thursday, November 3, 2022 at 3:37:43 PM UTC-4, Dave Nadler wrote:UUTs total. There will be an FPGA controlling each pair of UUTs, so 80 FPGAs in total that the PC needs to talk to.
On 11/2/2022 1:28 AM, Rick C wrote:
I have a test fixture that uses RS-232 to communicate with a PC. It actually uses the voltage levels of RS-232, even though this is from a USB cable on the PC, so it's only RS-232 for maybe four inches. lol
I'm redesigning the test fixtures to hold more units and fully automate a few features that presently requires an operator. There will now be 8 UUTs on each test fixture and I expect to have 10 to 20 test fixtures in a card rack. That's 80 to 160
they reply. The four FPGAs on a test fixture board could be connected in parallel easily enough. But I don't think I want to run TTL level signals between so many boards.
Rather than working on a way to mux 80 RS-232 interfaces, I'm thinking it would be better to either daisy chain, or connect in parallel all these devices. The protocol is master-slave where the master sends a command and the slaves are idle until
own start bit by overwriting the stop bit of the slave. I suppose someone, somewhere has dealt with this on the PC and has a solution that doesn't impact bus speed. I run the single test fixture version of this at about 100 kbps. I'm going to want as
I could do an RS-422 interface with a master to slave pair and a slave to master pair. The slaves do not speak until spoken to, so there will be no collisions.
RS-485 would allow all this to be over a single pair of wires. But the one big issue I see people complain about is getting PC software to not clobber the slaves, or I should say, to get the master to wait long enough that it's not clobbering it's
returns digital data which is crunched by the FPGA. This takes some small number of seconds and presently the protocol is to poll the status until it is done. That's a lot of messages, but it's not necessarily a slow point. The same test can be started
The tests are of two types, most of them are setting up a state and reading a signal. This can go pretty fast and doesn't take too many commands. Then there are the audio tests where the FPGA sends digital data to the UUT, which does it's thing and
allowing the transceivers to be used either way.
Still, I want to use RS-422 or RS-485 to deal with ground noise since this will be spread over multiple boards that don't have terribly solid grounds, just the power cable really.
I'm thinking out loud here as much as anything. I intended to simply ask if anyone had experience with RS-485 that would be helpful. Running two wires rather than eight would be a help. I'll probably use a 10 pin connector just to be on the safe side,
will be split into a master send bus and a slave reply bus. The master doesn't need to manage the tri-state output because it's the only talker. The slaves only talk when spoken to and the UART is in an FPGA, (no CPU), so it can manage the tri-stateHi Rick - I have an RS-485 system on my desk using an implementation of
the old Intel BitBus. Works fine for a handful of nodes, limited
distance, and very simple cabling - but only 62.5kbaud. Good solid
technology for 1994 when I designed it...
Why would you use RS-485 instead of CAN? A million chips out there
support CAN with no fuss, works at decent speeds over twisted pair, not
hard to use.
BTW, another option for interfacing to RS-485 from USB is XR21B1411
which is what I happen to have on my desk.
I'm using RS-422 because I don't need to learn how to use a "chip". It's the same serial protocol I'm using now, but instead of RS-232 voltage levels, it's RS-422 differential. The "change" is really the fact that it's not just one slave. So the bus
CAN bus might be the greatest thing since sliced bread, but I am going to be slammed with work and I don't want to do anything I don't absolutely have to.would all still have to be done even if adding the CAN bus. The slaves still need to be selected/addressed.
A lot of people don't understand that this is nearly the same as what I'm using now and will only require a very minor modification to the message protocol, to allow the slaves to be selected/addressed. It would be hard to make it any simpler and this
Thanks for the suggestions. The part I'm worried about now are the more mechanical bits. I am thinking of using the Eurocard size so I can use the rack hardware, but I know very little about the bits and bobs. There will be no backplane, just cardguides and the front panels on the cards to hold them in place. I might put the cabling on the front panel to give it easy access, but then it needs machining of the front panel. I could simplify that by cutting out one large hole to expose all the
Cablestogo has 6 inch cables for $2.99 each. I'd like to keep them
a bit shorter, but that's probably not an issue.
On Friday, November 4, 2022 at 6:53:34 PM UTC-4, [email protected] wrote:terminator on the receiver, but not the driver and no provision to add a terminator to the driver.
Rick C <[email protected]> wrote:
How long is a piece of string? By keeping the interconnecting cables short, 4" or so, and a 5 foot cable from the PC, I don't expect problems with reflections. But it is prudent to allow for them anyway. The FTDI RS-422 cable seems to have a
It is pointless to add terminator to driver, there will be mismatch
anyway and resistor would just waste transmit power. Mismatch
at driver does not case trouble as long as ends are properly
terminated. And when driver is at the near end and there are no
other drivers, then it is enough to put termination only at the
far end. So FTDI cable seem to be doing exactly what is needed.
Yes, that's true for a single driver and multiple receivers. The point is that with multiple drivers, a terminator is needed at both ends of the cable. You have two ends to terminate, because drivers can be in the middle.
You could not use FTDI RS-422 cables in the arrangement I am implementing. Every receiver would add a 120 ohm load to the line. Good thing I only need one!
not an issue. Since the interconnections between cards will be about five feet as well, it's unlikely to be an issue. The entire network will look like a lumped load, with the propagation time on the order of the rise/fall time. Even adding in a secondOddly enough, the RS-485 cable has a terminator that can be connected by the user, but that would be running through the cable separately from the transceiver signals, so essentially stubbed! I guess at 1 Mbps, 5 feet is less than the rise time, so
They sell cables that have 5 m of cable, with a round trip of 30 ns or so.Closer to 50 ns due to lower speed in cable.
I think that would still not be significant in this application. The driver rise/fall times are 15 ns typ, 25 ns max.Termination is also to kill _multiple_ reflections. In low loss line
you can have bunch of reflection creating jitter. When jitter is
more than 10% of bit time serial communication tends to have significant number of errors. At 9600 or at 100000 bits/s with short line bit
time is long enough that jitter due to reflections in untermined
line does not matter. Also multidrop RS-485 is far from low loss,
each extra drop weakens signal, so reflections die faster than
in quality point-to-point line.
How do RS-485 drops "weaken" the signal? The load of an RS-485 device is very slight. The same result will happen with multiple receivers on RS-422.
I expect to be running at least 1 Mbps, possibly as high as 3 Mbps.
One thing I'm a bit confused about, is the wiring of the EIA/TIA 568B or 568A cables. Both standards are used, but as far as I can tell, the only difference is the colors! The green and orange twisted pairs are reversed on both ends, making thecables electrically identical, other than the colors used for a given pair. The only difference is, the different pairs have different twist pitch, to help reduce crosstalk. But the numbers are not specified in the spec, so I don't see how this could
Why would the color be an issue, to the point of creating two different specs???
Obviously I'm missing something. I will need to check a cable before I design the boards, lol.
Rick C <[email protected]> wrote:terminator on the receiver, but not the driver and no provision to add a terminator to the driver.
On Friday, November 4, 2022 at 6:53:34 PM UTC-4, [email protected] wrote:
Rick C <[email protected]> wrote:
How long is a piece of string? By keeping the interconnecting cables short, 4" or so, and a 5 foot cable from the PC, I don't expect problems with reflections. But it is prudent to allow for them anyway. The FTDI RS-422 cable seems to have a
It is pointless to add terminator to driver, there will be mismatch anyway and resistor would just waste transmit power. Mismatch
at driver does not case trouble as long as ends are properly
terminated. And when driver is at the near end and there are no
other drivers, then it is enough to put termination only at the
far end. So FTDI cable seem to be doing exactly what is needed.
Yes, that's true for a single driver and multiple receivers. The point is that with multiple drivers, a terminator is needed at both ends of the cable. You have two ends to terminate, because drivers can be in the middle.With 100 Ohm line driver in the middle sees two parts in parallel, so effectively 50 Ohm. Typical driver impedance is about 40 Ohm, so
while mismatched, mismath is not too bad. Also, with multiple
devices on the line there will be undesirable signals even if you
have termination at both ends.
In unterminated line there will be some loss, so after each reflection reflected signal will be weaker, in rough approximation multiplied
by some number a < 1 (say 0.8). After n reflections signal will
be multiplied by a^n and for large enough n will become negligible. Termination at given end with 1% resistor means that about 2% will
be reflected (due to imperfection). This 2% is likely to be negligible.
If transmitter is in the middle, there is still reflection at the
end opposite to termination and at the transmitter. But mismatch
at transmitter is not bad and the corresponding parameter a is
much smaller than in unterminated case. So termination at one
end reduces number of problematic reflections probably about 2-4
times. Which means that you can increase transfer rate by
similar factor. Of course, termintion at both ends is better,
but in multidrop case speed will be lower than in point-to-point
link.
You could not use FTDI RS-422 cables in the arrangement I am implementing. Every receiver would add a 120 ohm load to the line. Good thing I only need one!Well, multiple receivers on RS-422 have limited usefulness (AFAIK your
use case is called 4-wire RS-485), so no wonder that FTDI does not
support it. Maybe they have something more expensive that is
doing what you want.
so not an issue. Since the interconnections between cards will be about five feet as well, it's unlikely to be an issue. The entire network will look like a lumped load, with the propagation time on the order of the rise/fall time. Even adding in aOddly enough, the RS-485 cable has a terminator that can be connected by the user, but that would be running through the cable separately from the transceiver signals, so essentially stubbed! I guess at 1 Mbps, 5 feet is less than the rise time,
They sell cables that have 5 m of cable, with a round trip of 30 ns or so.Closer to 50 ns due to lower speed in cable.
I think that would still not be significant in this application. The driver rise/fall times are 15 ns typ, 25 ns max.Termination is also to kill _multiple_ reflections. In low loss line
you can have bunch of reflection creating jitter. When jitter is
more than 10% of bit time serial communication tends to have significant number of errors. At 9600 or at 100000 bits/s with short line bit
time is long enough that jitter due to reflections in untermined
line does not matter. Also multidrop RS-485 is far from low loss,
each extra drop weakens signal, so reflections die faster than
in quality point-to-point line.
How do RS-485 drops "weaken" the signal? The load of an RS-485 device is very slight. The same result will happen with multiple receivers on RS-422.That is general thing, not specific to RS-485. If RS-485 receiver
puts 24 kOhm load on line, that is about 0.4% of line impedance.
When signal passes past receiver there is corresponding power loss.
There is also second effect: receiver created discontinuity, so
there is reflection. And beside resitive part receiver impedance
has also reactive part which means that discontinuity and reflection
is bigger than implied by receiver resistance. With lower load
recevier effect is smaller, but still there is fraction of percent
lost or reflected. Single loss is "very slight", but they add up
and increase effective line loss: with single receiver reflecting/losing
0.5 after 40 receivers 20% of signal is gone. This 20% effectively
adds to normal line loss.
I expect to be running at least 1 Mbps, possibly as high as 3 Mbps.You probably should check if you can get such rate with short messages.
If did little experiment using CH340 and CP2104. That was bi-drectional
TTL level serial connection using 15 cm wires. Slave echoed each
received character after mangling it a little (so I knew that it
really came from the slave and not from some echo in software stack).
I had trouble running CH340 above 460800 (that could be limit of program that I used). But using 1 character messages 10000 round trips took
about 7s, with small influence from serial speed (almost the same
result at 115200 and 230400). Also increasing message to 5 bytes
gave essentially the same number of _messages_.
CP2104 was better, here I could go up to 2000000. Using 5 byte
messages 10000 round trips needed 2.5s up to 1500000, at
2000000 time dropped to about 1.9. When I increased message
to 10 bytes it was back about 2.5s.
I must admit that ATM I am not sure what this means. But this 2.5s
looks significant: this means 4000 round trips per second, which
is 8000 messages, which in turn is number of USB cycles. So,
it seems that normally smallish messages need USB cycle (125 uS)
to get trough USB bus. It seems that sometimes more than one
message may go trough in a cycle (giving smaller times that I
observed), but it is not clear if one can do significantly better.
And CH340 shows that it may be much worse.
FTDI is claimed to be very good, so maybe it is better, but I would
not count on this without checking. Actually, I remember folks
complaining that they needed more than millisecond to get message
trough USB-serial.
OTOH, your description suggest that you should be able to do what
you want with much smaller message traffic, so maybe USB-serial
speed is enough for you.
cables electrically identical, other than the colors used for a given pair. The only difference is, the different pairs have different twist pitch, to help reduce crosstalk. But the numbers are not specified in the spec, so I don't see how this couldOne thing I'm a bit confused about, is the wiring of the EIA/TIA 568B or 568A cables. Both standards are used, but as far as I can tell, the only difference is the colors! The green and orange twisted pairs are reversed on both ends, making the
Why would the color be an issue, to the point of creating two different specs???
Obviously I'm missing something. I will need to check a cable before I design the boards, lol.You may be missing fact that most folks installing network cabling
do not know about transmission lines and reasons for matching pairs.
And even for folks that understand theory, it is easier to check
that colors are in position prescribed in the norm, than to check
pairs. So, colors matter because using colors folks can get correct connetion without too much thinking.
Why two specs? I think
that this is artifact of history and way that standard bodies work.
When half of industry is using one way and other half is using
different but equally good way standard body can not say that
one half is wrong, they must allow both ways.
On Friday, November 4, 2022 at 12:36:51 PM UTC-4, David Brown wrote:bit. There is no need for the bus to be idle in the sense of no data being sent. If an RS-485 or RS-422 bus is biased for undriven times, there is no need for the driver to be on through the full stop bit. Once the stop bit has driven high, it can be
On 04/11/2022 15:37, pozz wrote:
Il 04/11/2022 10:49, David Brown ha scritto:Communication is about /reliably/ transferring data between devices.
On 04/11/2022 08:45, pozz wrote:
Il 03/11/2022 16:26, David Brown ha scritto:
On 03/11/2022 14:00, pozz wrote:
Il 03/11/2022 12:42, David Brown ha scritto:
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown >>>>>>>>> wrote:
On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown >>>>>>>>>>> wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bit >>>>>>>> (typically sub-slot 9 of 16). The first transmitter will beDo you mean that RX interrupt triggers in the middle of the stop >>>>>>> bit and not at the end? Interesting, but are you sure this is the >>>>>>> case for every UART implemented in MCUs?
disabled at the end of the stop bit, and the next transmitter must >>>>>>>> not enable its driver until after that point - it must wait at >>>>>>>> least half a bit time after reception before starting
transmission. (It can wait longer without trouble, which is why >>>>>>>> faster baud rates are less likely to involve any complications here.) >>>>>>>
Of course I'm not sure - there are a /lot/ of MCU manufacturers!
UART receivers usually work in the same way, however. They have a >>>>>> sample clock running at 16 times the baud clock. The start bit is >>>>>> edge triggered to give the start of the character frame. Then each >>>>>> bit is sampled in the middle of its time slot - usually at subbit
slots 7, 8, and 9 with majority voting. So the stop bit is
recognized by subbit slot 9 of the tenth bit (assuming 8-bit, no
parity) - the voltage on the line after that is irrelevant. (Even >>>>>> when you have two stop bits, receivers never check the second stop >>>>>> bit - it affects transmit timing only.) What purpose would there be >>>>>> in waiting another 7 subbits before triggering the interrupt, DMA, >>>>>> or whatever?
There's no real purpose, but it's important to know exactly when the >>>>> RX interrupt is fired from the UART.
I think it is extremely rare that this is important. I can't think of >>>> a single occasion when I have thought it remotely relevant where in
the stop bit the interrupt comes.
Usually the next transmitter starts transmitting after receiving the >>>>> last byte of the previous transmitter (for example, the slave starts >>>>> replying to the master after receiving the complete message from it). >>>>>
No. Usually the next transmitter starts after receiving the last
byte, and /then a pause/. There will always be some handling time in
software, and may also include an explicit pause. Almost always you
will want to do at least a minimum of checking of the incoming data
before deciding on the next telegram to be sent out. But if you have
very fast handling in relation to the baud rate, you will want an
explicit pause too - protocols regularly specify a minimum pause (such >>>> as 3.5 character times for Modbus RTU), and you definitely want it to
be at least one full character time to ensure no listener gets
hopelessly out of sync.
In theory, if all the nodes on the bus were able to change direction in
hardware (exactly at the end of the stop bit), you will not be forced to >>> introduce any delay in the transmission.
Asynchronous serial communication is about doing that despite slight
differences in clock rates, differences in synchronisation, differences
in startup times, etc. If you don't have idle pauses, you have almost
zero chance of staying in sync across the nodes - and no chance at all
of recovery when that happens. /Every/ successful serial protocol has
pauses between frames - long enough pauses that the idle time could not
possibly be part of a normal full speed frame. That does not just apply
to UART protocols, or even just to asynchronous protocols. The pause
does not have to be as long as 3.5 characters, but you need a pause -
just as you need other error recovery handling.
The "idle" pauses you talk about are accommodated with the start and stop bits in the async protocol. Every character is sent with a start bit which starts the timing. The stop bit is the "fluff" time for the next character to align to the next start
Many times I'm the author of a custom protocol because some nodes on aNegligible means of no significance in comparison to the delays you have
shared bus, so I'm not forced to follow any specifications. When I
didn't introduce any delay in the transmission, I sometimes faced this
issue. In my experience, the bus is heterogeneous enough to have a fast
replying slave to a slow master.
Now I think of the issue related to a transmitter that delays a
little to turn around the direction of its transceiver, from TX to
RX. Every transmitter on the bus should take into account this delay >>>>> and avoid starting transmission too soon.
They should, yes. The turnaround delay should be negligible in this
day and age - if not, your software design is screwed or you have
picked the wrong hardware. (Of course, you don't always get the
choice of hardware you want, and programmers are often left to find
ways around hardware design flaws.)
Negligible doesn't mean anything.
anyway - either intentional delays in order to separate telegrams and
have a reliable communication, or unavoidable delays due to software
processing.
The software on the PC is not managing the bus drivers. So software delays are not relevant to bus control timing.
If thre's a poor 8 bit PIC (previousNo, you won't - not unless you are doing something silly in your timing
transmitter) clocked at 8MHz that changes direction in TXC interrupt
while other interrupts are active, and there's a Cortex-M4 clocked at
200MHz (next transmitter), you will encounter this issue.
such as failing to use appropriate pauses or thinking that 10 µs
turnarounds are a good idea at 9600 baud. And I did specify picking
sensible hardware - 8-bit PICs were are terrible choice 20 years ago for
anything involving high speed, and they have not improved. (Again -
sometimes you don't have control of the hardware, and sometimes there
can be other overriding reasons for picking something. But if your
hardware is limited, you have to take that into account.)
This is more evident if, as you are saying, the Cortex-M4 is able toSorry, but I cannot see any situation where that would happen in a
start processing the message from the PIC at the midpoint of last stop
bit, while the PIC disables its driver at the *end* of the stop bit plus >>> an additional delay caused by interrupts handling.
In this cases the half bit time is not negligible and must be added to
the transmission delay.
well-designed communication system.
Oh, and it is actually essential that the receiver considers the
character finished half-way through the stop bit, and not at the end.
UART communication is intended to work despite small differences in the
baud rate - up to nearly 5% total error. By the time the receiver is
half way through the received stop bit, and has identified it is valid,
the sender could be finished the stop bit as its clock is almost 5%
faster (50% bit time over the full 10 bits). The receiver has to be in
the "watch for falling edge of start bit" state at this point, ready for
the transmitter to start its next frame.
Yes, why would it not be? This is why there's no need for additional delays or "gaps" in the protocol for an async interface.
On Friday, November 4, 2022 at 5:49:42 AM UTC-4, David Brown wrote:main CPU to handle this timing. There's no reason to expect the driver disable to take more than a fraction of a bit time, so the "UART" needs a timing signal to indicate when the stop bit has been completed.
On 04/11/2022 08:45, pozz wrote:
Il 03/11/2022 16:26, David Brown ha scritto:I think it is extremely rare that this is important. I can't think of a
On 03/11/2022 14:00, pozz wrote:
Il 03/11/2022 12:42, David Brown ha scritto:
On 03/11/2022 00:27, Rick C wrote:
On Wednesday, November 2, 2022 at 4:49:16 PM UTC-4, David Brown wrote: >>>>>>>> On 02/11/2022 20:20, Rick C wrote:
On Wednesday, November 2, 2022 at 5:28:21 AM UTC-4, David Brown >>>>>>>>> wrote:
On 02/11/2022 06:28, Rick C wrote:
You are correct that reception is in the middle of the stop bit
(typically sub-slot 9 of 16). The first transmitter will be
disabled at the end of the stop bit, and the next transmitter must >>>>>> not enable its driver until after that point - it must wait at least >>>>>> half a bit time after reception before starting transmission. (It >>>>>> can wait longer without trouble, which is why faster baud rates are >>>>>> less likely to involve any complications here.)
Do you mean that RX interrupt triggers in the middle of the stop bit >>>>> and not at the end? Interesting, but are you sure this is the case
for every UART implemented in MCUs?
Of course I'm not sure - there are a /lot/ of MCU manufacturers!
UART receivers usually work in the same way, however. They have a
sample clock running at 16 times the baud clock. The start bit is
edge triggered to give the start of the character frame. Then each
bit is sampled in the middle of its time slot - usually at subbit
slots 7, 8, and 9 with majority voting. So the stop bit is recognized >>>> by subbit slot 9 of the tenth bit (assuming 8-bit, no parity) - the
voltage on the line after that is irrelevant. (Even when you have two >>>> stop bits, receivers never check the second stop bit - it affects
transmit timing only.) What purpose would there be in waiting another >>>> 7 subbits before triggering the interrupt, DMA, or whatever?
There's no real purpose, but it's important to know exactly when the RX
interrupt is fired from the UART.
single occasion when I have thought it remotely relevant where in the
stop bit the interrupt comes.
Usually the next transmitter starts transmitting after receiving theNo. Usually the next transmitter starts after receiving the last byte,
last byte of the previous transmitter (for example, the slave starts
replying to the master after receiving the complete message from it).
and /then a pause/. There will always be some handling time in
software, and may also include an explicit pause. Almost always you
will want to do at least a minimum of checking of the incoming data
before deciding on the next telegram to be sent out. But if you have
very fast handling in relation to the baud rate, you will want an
explicit pause too - protocols regularly specify a minimum pause (such
as 3.5 character times for Modbus RTU), and you definitely want it to be
at least one full character time to ensure no listener gets hopelessly
out of sync.
Now I think of the issue related to a transmitter that delays a littleThey should, yes. The turnaround delay should be negligible in this day
to turn around the direction of its transceiver, from TX to RX. Every
transmitter on the bus should take into account this delay and avoid
starting transmission too soon.
and age - if not, your software design is screwed or you have picked the
wrong hardware. (Of course, you don't always get the choice of hardware
you want, and programmers are often left to find ways around hardware
design flaws.)
Implementing an explicit delay (or being confident that your telegram
So I usually implement a short delay before starting a new message
transmission. If the maximum expected delay of moving the direction from >>> TX to RX is 10us, I could think to use a 10us delay, but this is wrong
in your assumption.
handling code takes long enough) is a good idea.
If the RX interrupt is at the middle of the stop bit, I should delay the >>> new transmission of 10us + half of bit time. With 9600 this is 52us that >>> is much higher than 10us.I made no such assumptions about timings. The figures I gave were for
using a USB 2 based interface on a PC, where the USB polling timer is at
8 kHz, or 125 µs. That is half a bit time for 4 Kbaud. (I had doubled
the frequency instead of halving it and said the baud had to be above 16
kBaud - that shows it's good to do your own calculations and not trust
others blindly!). At 1 MBaud (the suggested rate), the absolute fastest
the PC could turn around the bus would be 12 character times - half a
stop bit is irrelevant.
You are making an assumption of implementation. There is a processor in the USB cable that is implementing the UART. The driver enable control is most likely is implemented there. It would be pointless and very subject to failure, to require the
The timing issue is not about loading another character into the transmit FIFO. It's about controlling the driver enable.
indication from the UART needs to be the end of the stop bit, not the middle.If you have a 9600 baud RS-485 receiver and you have a delay of 10 µs
between reception of the last bit and the start of transmission of the
next message, your code is wrong - by nearly two orders of magnitude.
It is that simple.
If we take Modbus RTU as an example, you should be waiting 3.5 * 10 /
9600 seconds at a minimum - 3.65 /milli/seconds. If you are concerned
about exactly where the receive interrupt comes in the last stop bit,
add another half bit time and you get 3.7 ms. The half bit time is
negligible.
Your numbers are only relevant to Modbus. The only requirement is that no two drivers are on the bus at the same time, which requires zero delay from the end of the previous stop bit and the beginning of the next start bit. This is why the timing
I know the next transmitter should make some processing of the previousSo put in a delay. An /appropriate/ delay.
received message, prepare and buffer the new message to transmit, so the >>> delay is somewhat automatic, but in many cases I have small 8-bits PICs
and full-futured Linux box on the same bus and the Linux could be very
fast to start the new transmission.
You are thinking software, like most people do.
The slaves will be in logic, so the UART will have timing information relevant to the end of bits. I don't care how the master does it. The FTDI cable is alleged to "just work". Nonetheless, I will be providing for separate send and receive buses (or call it master/slave buses). Only one slave will be addressed at a time, so no collisions there, and the master can't collide with itself.
terminator on the receiver, but not the driver and no provision to add a terminator to the driver.If you are pushing the limits of a bus, in terms of load, distance,
speed, cable characteristics, etc., then you need to do such
calculations carefully and be precise in your specification of
components, cables, topology, connectors, etc. For many buses in
practice, they will work fine using whatever resistor you pull out your
box of random parts. For a testbench, you are going to go for something
between these extremes.
How long is a piece of string? By keeping the interconnecting cables short, 4" or so, and a 5 foot cable from the PC, I don't expect problems with reflections. But it is prudent to allow for them anyway. The FTDI RS-422 cable seems to have a
Oddly enough, the RS-485 cable has a terminator that can be connected by the user, but that would be running through the cable separately from the transceiver signals, so essentially stubbed! I guess at 1 Mbps, 5 feet is less than the rise time, sonot an issue. Since the interconnections between cards will be about five feet as well, it's unlikely to be an issue. The entire network will look like a lumped load, with the propagation time on the order of the rise/fall time. Even adding in a
They sell cables that have 5 m of cable, with a round trip of 30 ns or so. I think that would still not be significant in this application. The driver rise/fall times are 15 ns typ, 25 ns max.
Rick C <[email protected]> writes:
Cablestogo has 6 inch cables for $2.99 each. I'd like to keep them
a bit shorter, but that's probably not an issue.
I thought there was a minimum length for ethernet cables because they
have to have certain RF characteristics at 100mhz or 1ghz frequencies.
I didn't realize they even came as short as 6 inches. Either way
though, it shouldn't be an issue for your purposes.
On 04/11/2022 18:11, Rick C wrote:bit. There is no need for the bus to be idle in the sense of no data being sent. If an RS-485 or RS-422 bus is biased for undriven times, there is no need for the driver to be on through the full stop bit. Once the stop bit has driven high, it can be
On Friday, November 4, 2022 at 12:36:51 PM UTC-4, David Brown wrote:
Communication is about /reliably/ transferring data between devices.
Asynchronous serial communication is about doing that despite slight
differences in clock rates, differences in synchronisation, differences >> in startup times, etc. If you don't have idle pauses, you have almost
zero chance of staying in sync across the nodes - and no chance at all
of recovery when that happens. /Every/ successful serial protocol has
pauses between frames - long enough pauses that the idle time could not >> possibly be part of a normal full speed frame. That does not just apply >> to UART protocols, or even just to asynchronous protocols. The pause
does not have to be as long as 3.5 characters, but you need a pause -
just as you need other error recovery handling.
The "idle" pauses you talk about are accommodated with the start and stop bits in the async protocol. Every character is sent with a start bit which starts the timing. The stop bit is the "fluff" time for the next character to align to the next start
There are two levels of framing here, and two types of pauses.
For UART communication, there is the "character frame" and the stop bit
acts as a pause between characters. This is to give a minimum time to
allow re-synchronisation of the clock timing at the receiver. It also
forms, along with the start bit, a guaranteed edge for this re-synchronisation. More sophisticated serial protocols (CAN, Ethernet, etc.) do not need this because they have other methods of guaranteeing transitions and allowing the receiver to re-synchronise regularly - thus they do not need framing or idling at the character or byte level.
But you always want framing and idling between message frames at a
higher level. You always have an idle period that is longer than any
valid character or part of a message.
In UART communication, this is handled at the protocol level rather than
the hardware (though some UART hardware may have "idle detect" signals
when more than 11 bits of high level are seen in a row). Some
UART-based protocols also use a "break" signal between frames - that is
a string of at least 11 bits of low level.
If you do not have such pauses, and a receiver is out of step,
it has no
way to get into synchronisation again. Maybe you get lucky, but
basically all it is seeing is a stream of high and low bits with no
absolute indicator of position - and no way to tell what might be the
start bit of a new character (rather than a 1 bit then a 0 bit within a character), never mind the start of a message.
Usually you get enough pauses naturally in the communication, with
delays between reception and reply. But if you don't have them, you
must add them. Otherwise your communication will be too fragile to use
in practice. You /need/ idle gaps to be able to resynchronise reliably
in the face of errors (and there is /always/ a risk of errors).
Oh, and it is actually essential that the receiver considers the
character finished half-way through the stop bit, and not at the end.
UART communication is intended to work despite small differences in the >> baud rate - up to nearly 5% total error. By the time the receiver is
half way through the received stop bit, and has identified it is valid, >> the sender could be finished the stop bit as its clock is almost 5%
faster (50% bit time over the full 10 bits). The receiver has to be in
the "watch for falling edge of start bit" state at this point, ready for >> the transmitter to start its next frame.
Yes, why would it not be? This is why there's no need for additional delays or "gaps" in the protocol for an async interface.
It will be in the right state at the right time, as long as it enters it when the stop bit is identified (half-way through the stop bit) rather
than artificially waiting for the end of the bit time.
You need gaps in the character stream at a higher level, for error recovery.
On 04/11/2022 16:40, Rick C wrote:CPU to handle this timing. There's no reason to expect the driver disable to take more than a fraction of a bit time, so the "UART" needs a timing signal to indicate when the stop bit has been completed.
On Friday, November 4, 2022 at 5:49:42 AM UTC-4, David Brown wrote:
I made no such assumptions about timings. The figures I gave were for
using a USB 2 based interface on a PC, where the USB polling timer is at >> 8 kHz, or 125 µs. That is half a bit time for 4 Kbaud. (I had doubled
the frequency instead of halving it and said the baud had to be above 16 >> kBaud - that shows it's good to do your own calculations and not trust
others blindly!). At 1 MBaud (the suggested rate), the absolute fastest >> the PC could turn around the bus would be 12 character times - half a
stop bit is irrelevant.
You are making an assumption of implementation. There is a processor in the USB cable that is implementing the UART. The driver enable control is most likely is implemented there. It would be pointless and very subject to failure, to require the main
I'm making the assumption that you are using appropriate hardware. No processor, just a USB device that has a "transmitter enable" signal on
its UART.
I'm getting the impression that you have never heard of such a UART
(either in a USB-to-UART device, or as a UART peripheral elsewhere), and assume software has to be involved in enabling and disabling the transmitter. Please believe me when I say such UARTs /do/ exist - and
the FTDI examples I keep giving are a case in point.
indication from the UART needs to be the end of the stop bit, not the middle.The timing issue is not about loading another character into the transmit FIFO. It's about controlling the driver enable.
Yes, and it is a /solved/ issue if you pick the right hardware.
If you have a 9600 baud RS-485 receiver and you have a delay of 10 µs
between reception of the last bit and the start of transmission of the
next message, your code is wrong - by nearly two orders of magnitude.
It is that simple.
If we take Modbus RTU as an example, you should be waiting 3.5 * 10 /
9600 seconds at a minimum - 3.65 /milli/seconds. If you are concerned
about exactly where the receive interrupt comes in the last stop bit,
add another half bit time and you get 3.7 ms. The half bit time is
negligible.
Your numbers are only relevant to Modbus. The only requirement is that no two drivers are on the bus at the same time, which requires zero delay from the end of the previous stop bit and the beginning of the next start bit. This is why the timing
A single transmitter, while sending a multi-character message, does not
need any delay between sending the full stop bit and starting the next
start bit. That is obvious. And that is why a "transmission complete"
signal comes at the end of the start bit sent on the transmitter side.
On the receiver side, the "byte received" signal comes in the /middle/
of the stop bit, as seen by the receiver, because that could be at the
/end/ of the stop bit as seen by the transmitter due to clock
differences. (It could also be at the /start/ of the stop bit as seen
by the transmitter.) The receiver has to prepare for the next incoming
start bit as soon as it identifies the stop bit.
But you want an extra delay of at least 11 bits (a character frame plus
a buffer for clock speed differences) between messages - whether they
are from the same transmitter or a different transmitter - to allow resynchronisation if something has gone wrong.
I've explained in other posts why inter-message pauses are needed for reliable UART communication protocols. They don't /need/ to be as long
as 35 bit times as Modbus specifies - 11 bit times is the minimum. If
you don't understand this by now, then we should drop this point.
So put in a delay. An /appropriate/ delay.
You are thinking software, like most people do.It doesn't matter whether things are software, hardware, or something in between.
call it master/slave buses). Only one slave will be addressed at a time, so no collisions there, and the master can't collide with itself.The slaves will be in logic, so the UART will have timing information relevant to the end of bits. I don't care how the master does it. The FTDI cable is alleged to "just work". Nonetheless, I will be providing for separate send and receive buses (or
Yes, with the bus you have described, and the command/response protocol
you have described, there should be no problems with multiple
transmitters on the bus, and you have plenty of inter-message idle periods.
However, this Usenet thread has been mixing posts from different people,
and discussions of different kinds of buses and protocols - not just the solution you picked (which, as I have said before, should work fine). I think this mixing means that people are sometimes talking at cross-purposes.
terminator on the receiver, but not the driver and no provision to add a terminator to the driver.If you are pushing the limits of a bus, in terms of load, distance,
speed, cable characteristics, etc., then you need to do such
calculations carefully and be precise in your specification of
components, cables, topology, connectors, etc. For many buses in
practice, they will work fine using whatever resistor you pull out your >> box of random parts. For a testbench, you are going to go for something >> between these extremes.
How long is a piece of string? By keeping the interconnecting cables short, 4" or so, and a 5 foot cable from the PC, I don't expect problems with reflections. But it is prudent to allow for them anyway. The FTDI RS-422 cable seems to have a
There is no point in having a terminator at a driver (unless you are
talking about very high speed signals with serial resistors for slope control). You will want to add a terminator at the far end of both
buses. This will give you a single terminator on the PC-to-slave bus,
which is fine as it is fixed direction, and two terminators on the slave-to-PC bus, which is appropriate as it has no fixed direction.
(I agree that your piece of string is of a size that should work fine without reflections being a concern.)not an issue. Since the interconnections between cards will be about five feet as well, it's unlikely to be an issue. The entire network will look like a lumped load, with the propagation time on the order of the rise/fall time. Even adding in a second
Oddly enough, the RS-485 cable has a terminator that can be connected by the user, but that would be running through the cable separately from the transceiver signals, so essentially stubbed! I guess at 1 Mbps, 5 feet is less than the rise time, so
They sell cables that have 5 m of cable, with a round trip of 30 ns or so. I think that would still not be significant in this application. The driver rise/fall times are 15 ns typ, 25 ns max.
The speed of a signal in a copper cable is typically about 70% of the
speed of light, giving a minimum round-trip time closer to 45 ns than 30
ns. Not that it makes any difference here.
On Saturday, November 5, 2022 at 7:47:59 AM UTC-4, David Brown wrote:CPU to handle this timing. There's no reason to expect the driver disable to take more than a fraction of a bit time, so the "UART" needs a timing signal to indicate when the stop bit has been completed.
On 04/11/2022 16:40, Rick C wrote:
On Friday, November 4, 2022 at 5:49:42 AM UTC-4, David Brown wrote:
I made no such assumptions about timings. The figures I gave were for
using a USB 2 based interface on a PC, where the USB polling timer is at >>>> 8 kHz, or 125 µs. That is half a bit time for 4 Kbaud. (I had doubled >>>> the frequency instead of halving it and said the baud had to be above 16 >>>> kBaud - that shows it's good to do your own calculations and not trust >>>> others blindly!). At 1 MBaud (the suggested rate), the absolute fastest >>>> the PC could turn around the bus would be 12 character times - half a
stop bit is irrelevant.
You are making an assumption of implementation. There is a processor in the USB cable that is implementing the UART. The driver enable control is most likely is implemented there. It would be pointless and very subject to failure, to require the main
I'm making the assumption that you are using appropriate hardware. No
processor, just a USB device that has a "transmitter enable" signal on
its UART.
How can there not be a processor? I'm using a split bus, with the PC master driving all the slave receivers and all the slave transmitters sharing the PC receive bus.
Is the PC not a processor?
The slaves have no USB.
device, because it's not tristateable.I'm getting the impression that you have never heard of such a UART
(either in a USB-to-UART device, or as a UART peripheral elsewhere), and
assume software has to be involved in enabling and disabling the
transmitter. Please believe me when I say such UARTs /do/ exist - and
the FTDI examples I keep giving are a case in point.
You are not being clear. I don't know and don't care what is inside the FTDI device. That's just magic to me, or it's like something inside the black hole, unknowable. More importantly, there is no transmitter enable on the RS-422 driver in the FTDI
indication from the UART needs to be the end of the stop bit, not the middle. >>>The timing issue is not about loading another character into the transmit FIFO. It's about controlling the driver enable.Yes, and it is a /solved/ issue if you pick the right hardware.
If you have a 9600 baud RS-485 receiver and you have a delay of 10 µs >>>> between reception of the last bit and the start of transmission of the >>>> next message, your code is wrong - by nearly two orders of magnitude.
It is that simple.
If we take Modbus RTU as an example, you should be waiting 3.5 * 10 /
9600 seconds at a minimum - 3.65 /milli/seconds. If you are concerned
about exactly where the receive interrupt comes in the last stop bit,
add another half bit time and you get 3.7 ms. The half bit time is
negligible.
Your numbers are only relevant to Modbus. The only requirement is that no two drivers are on the bus at the same time, which requires zero delay from the end of the previous stop bit and the beginning of the next start bit. This is why the timing
A single transmitter, while sending a multi-character message, does not
need any delay between sending the full stop bit and starting the next
start bit. That is obvious. And that is why a "transmission complete"
signal comes at the end of the start bit sent on the transmitter side.
??? Are you talking about the buffer management signals for the software?
On the receiver side, the "byte received" signal comes in the /middle/
of the stop bit, as seen by the receiver, because that could be at the
/end/ of the stop bit as seen by the transmitter due to clock
differences. (It could also be at the /start/ of the stop bit as seen
by the transmitter.) The receiver has to prepare for the next incoming
start bit as soon as it identifies the stop bit.
Again, this depends entirely on what this signal is used for. For entering the state of detecting the next start bit, yes, that is the perceived middle of the stop bit.
But you want an extra delay of at least 11 bits (a character frame plus
a buffer for clock speed differences) between messages - whether they
are from the same transmitter or a different transmitter - to allow
resynchronisation if something has gone wrong.
Again, you seem to not understand the use case.
The split bus never has messages back to back on the same pair. It gets confusing because so many people have tried to talk up RS-485 using a single pair. In that case, everything is totally different. Slaves need to wait until the driver hasstopped driving the bus, which means an additional bit time to account for timing errors. But RS-485 is not being used. Each bus is simplex, implementing a half-duplex protocol on the two buses.
I've explained in other posts why inter-message pauses are needed for
reliable UART communication protocols. They don't /need/ to be as long
as 35 bit times as Modbus specifies - 11 bit times is the minimum. If
you don't understand this by now, then we should drop this point.
You are assuming a need for error tolerance. But a munged message is the problem, not resyncing. A protocol to detect an error and retransmit is very messy. I've tried that before and it messes up the protocol badly.
It doesn't matter whether things are software, hardware, or something inSo put in a delay. An /appropriate/ delay.
You are thinking software, like most people do.
between.
Of course it does. Since the slaves are all logic, there is no need for delays, at all. The slave driver can be enabled at any time the message has been received and the reply is ready to go.
call it master/slave buses). Only one slave will be addressed at a time, so no collisions there, and the master can't collide with itself.The slaves will be in logic, so the UART will have timing information relevant to the end of bits. I don't care how the master does it. The FTDI cable is alleged to "just work". Nonetheless, I will be providing for separate send and receive buses (or
Yes, with the bus you have described, and the command/response protocol
you have described, there should be no problems with multiple
transmitters on the bus, and you have plenty of inter-message idle periods. >>
However, this Usenet thread has been mixing posts from different people,
and discussions of different kinds of buses and protocols - not just the
solution you picked (which, as I have said before, should work fine). I
think this mixing means that people are sometimes talking at cross-purposes.
Yes, it gets confusing.
terminator on the receiver, but not the driver and no provision to add a terminator to the driver.If you are pushing the limits of a bus, in terms of load, distance,
speed, cable characteristics, etc., then you need to do such
calculations carefully and be precise in your specification of
components, cables, topology, connectors, etc. For many buses in
practice, they will work fine using whatever resistor you pull out your >>>> box of random parts. For a testbench, you are going to go for something >>>> between these extremes.
How long is a piece of string? By keeping the interconnecting cables short, 4" or so, and a 5 foot cable from the PC, I don't expect problems with reflections. But it is prudent to allow for them anyway. The FTDI RS-422 cable seems to have a
There is no point in having a terminator at a driver (unless you are
talking about very high speed signals with serial resistors for slope
control). You will want to add a terminator at the far end of both
buses. This will give you a single terminator on the PC-to-slave bus,
which is fine as it is fixed direction, and two terminators on the
slave-to-PC bus, which is appropriate as it has no fixed direction.
It does if you are using it in a shared bus with multiple drivers. The line should still be organized as linear with minimal stubs and a terminator on each end. This is not my plan, so maybe I should stop discussing it.
not an issue. Since the interconnections between cards will be about five feet as well, it's unlikely to be an issue. The entire network will look like a lumped load, with the propagation time on the order of the rise/fall time. Even adding in a second(I agree that your piece of string is of a size that should work fine
without reflections being a concern.)
Oddly enough, the RS-485 cable has a terminator that can be connected by the user, but that would be running through the cable separately from the transceiver signals, so essentially stubbed! I guess at 1 Mbps, 5 feet is less than the rise time, so
year. I may need to get with the factory and see if they can supply me directly.The speed of a signal in a copper cable is typically about 70% of the
They sell cables that have 5 m of cable, with a round trip of 30 ns or so. I think that would still not be significant in this application. The driver rise/fall times are 15 ns typ, 25 ns max.
speed of light, giving a minimum round-trip time closer to 45 ns than 30
ns. Not that it makes any difference here.
The problem I have now is finding parts to use for this. These devices seem to be in a catagory that are hit hard by the shortage. My product uses the SN65C1168EPW, which is very hard to find in quantity. My customer has mentioned 18,000 units next
On 05/11/2022 18:23, Rick C wrote:main CPU to handle this timing. There's no reason to expect the driver disable to take more than a fraction of a bit time, so the "UART" needs a timing signal to indicate when the stop bit has been completed.
On Saturday, November 5, 2022 at 7:47:59 AM UTC-4, David Brown wrote:
On 04/11/2022 16:40, Rick C wrote:
On Friday, November 4, 2022 at 5:49:42 AM UTC-4, David Brown wrote:
I made no such assumptions about timings. The figures I gave were for >>>> using a USB 2 based interface on a PC, where the USB polling timer is at
8 kHz, or 125 µs. That is half a bit time for 4 Kbaud. (I had doubled >>>> the frequency instead of halving it and said the baud had to be above 16
kBaud - that shows it's good to do your own calculations and not trust >>>> others blindly!). At 1 MBaud (the suggested rate), the absolute fastest >>>> the PC could turn around the bus would be 12 character times - half a >>>> stop bit is irrelevant.
You are making an assumption of implementation. There is a processor in the USB cable that is implementing the UART. The driver enable control is most likely is implemented there. It would be pointless and very subject to failure, to require the
I'm making the assumption that you are using appropriate hardware. No
processor, just a USB device that has a "transmitter enable" signal on
its UART.
How can there not be a processor? I'm using a split bus, with the PC master driving all the slave receivers and all the slave transmitters sharing the PC receive bus.
Is the PC not a processor?Sure, the PC is a processor. It sends a command to the USB device,
saying "send these N bytes of data out on the UART ...".
The USB device is /not/ a processor - it is a converter between USB and UART. And it is the USB device that controls the transmit enable signal
to the RS-485/RS-422 driver. There is no software on any processor
handling the transmit enable signal - the driver is enabled precisely
when the USB to UART device is sending data on the UART.
The slaves have no USB.
device, because it's not tristateable.I'm getting the impression that you have never heard of such a UART
(either in a USB-to-UART device, or as a UART peripheral elsewhere), and >> assume software has to be involved in enabling and disabling the
transmitter. Please believe me when I say such UARTs /do/ exist - and
the FTDI examples I keep giving are a case in point.
You are not being clear. I don't know and don't care what is inside the FTDI device. That's just magic to me, or it's like something inside the black hole, unknowable. More importantly, there is no transmitter enable on the RS-422 driver in the FTDI
As I mentioned earlier, this thread is getting seriously mixed-up. The transmit enable discussion started with /RS-485/ - long before you
decided to use a hybrid bus and a RS-422 cable. You were concerned
about how the PC controlled the transmitter enable for the RS-485
driver, and I have been trying to explain how this works when you use a decent UART device. You only confuse yourself when you jump to
discussing RS-422 here, in this bit of the conversation.
The FTDI USB to UART chip (or chips - they have several) provides a "transmitter enable" signal that is active with exactly the right timing
for RS-485. This is provided automatically, in hardware - no software involved. If you connect one of these chips to an RS-485 driver, you immediately have a "perfect" RS-485 interface with automatic direction control. If you connect one of these chips to an RS-422 driver, you
don't need direction control as RS-422 has two fixed-direction pairs.
If you buy a pre-built cable from FTDI, it will have one of these driver chips connected appropriately.
indication from the UART needs to be the end of the stop bit, not the middle.The timing issue is not about loading another character into the transmit FIFO. It's about controlling the driver enable.Yes, and it is a /solved/ issue if you pick the right hardware.
If you have a 9600 baud RS-485 receiver and you have a delay of 10 µs >>>> between reception of the last bit and the start of transmission of the >>>> next message, your code is wrong - by nearly two orders of magnitude. >>>> It is that simple.
If we take Modbus RTU as an example, you should be waiting 3.5 * 10 / >>>> 9600 seconds at a minimum - 3.65 /milli/seconds. If you are concerned >>>> about exactly where the receive interrupt comes in the last stop bit, >>>> add another half bit time and you get 3.7 ms. The half bit time is
negligible.
Your numbers are only relevant to Modbus. The only requirement is that no two drivers are on the bus at the same time, which requires zero delay from the end of the previous stop bit and the beginning of the next start bit. This is why the timing
driving the bus, which means an additional bit time to account for timing errors. But RS-485 is not being used. Each bus is simplex, implementing a half-duplex protocol on the two buses.A single transmitter, while sending a multi-character message, does not >> need any delay between sending the full stop bit and starting the next
start bit. That is obvious. And that is why a "transmission complete"
signal comes at the end of the start bit sent on the transmitter side.
??? Are you talking about the buffer management signals for the software?
No.
On the receiver side, the "byte received" signal comes in the /middle/
of the stop bit, as seen by the receiver, because that could be at the
/end/ of the stop bit as seen by the transmitter due to clock
differences. (It could also be at the /start/ of the stop bit as seen
by the transmitter.) The receiver has to prepare for the next incoming
start bit as soon as it identifies the stop bit.
Again, this depends entirely on what this signal is used for. For entering the state of detecting the next start bit, yes, that is the perceived middle of the stop bit.
Yes.
But you want an extra delay of at least 11 bits (a character frame plus >> a buffer for clock speed differences) between messages - whether they
are from the same transmitter or a different transmitter - to allow
resynchronisation if something has gone wrong.
Again, you seem to not understand the use case.Yes, I understand your new use case, as well as the original discussions
and the side discussions. I don't think /you/ understand that there had
been a change, because you seem to imagine everything in the thread is
in reference to your current solution.
The split bus never has messages back to back on the same pair. It gets confusing because so many people have tried to talk up RS-485 using a single pair. In that case, everything is totally different. Slaves need to wait until the driver has stopped
I agree. I know how your solution works, and have said many times that
I think it sounds quite a good idea for the task in hand.
I've explained in other posts why inter-message pauses are needed for
reliable UART communication protocols. They don't /need/ to be as long
as 35 bit times as Modbus specifies - 11 bit times is the minimum. If
you don't understand this by now, then we should drop this point.
You are assuming a need for error tolerance. But a munged message is the problem, not resyncing. A protocol to detect an error and retransmit is very messy. I've tried that before and it messes up the protocol badly.
All communications have failures. Accept that as a principle, and
understand how to deal with it. It's not hard to do - it is certainly
much easier than trying to imagine and eliminate any possible cause of trouble.
It doesn't matter whether things are software, hardware, or something in >> between.So put in a delay. An /appropriate/ delay.
You are thinking software, like most people do.
Of course it does. Since the slaves are all logic, there is no need for delays, at all. The slave driver can be enabled at any time the message has been received and the reply is ready to go.
I'm sorry you don't understand, and I can't see how to explain it better than to say timing and delays are fundamental to the communication, not
the implementation.
or call it master/slave buses). Only one slave will be addressed at a time, so no collisions there, and the master can't collide with itself.The slaves will be in logic, so the UART will have timing information relevant to the end of bits. I don't care how the master does it. The FTDI cable is alleged to "just work". Nonetheless, I will be providing for separate send and receive buses (
terminator on the receiver, but not the driver and no provision to add a terminator to the driver.Yes, with the bus you have described, and the command/response protocol >> you have described, there should be no problems with multiple
transmitters on the bus, and you have plenty of inter-message idle periods.
However, this Usenet thread has been mixing posts from different people, >> and discussions of different kinds of buses and protocols - not just the >> solution you picked (which, as I have said before, should work fine). I >> think this mixing means that people are sometimes talking at cross-purposes.
Yes, it gets confusing.
There has, I think, been some interesting discussion despite the
confusion. I hope you have got something out of it too - and I am glad
that you have a bus solution that looks like it will work well for the purpose.
If you are pushing the limits of a bus, in terms of load, distance, >>>> speed, cable characteristics, etc., then you need to do such
calculations carefully and be precise in your specification of
components, cables, topology, connectors, etc. For many buses in
practice, they will work fine using whatever resistor you pull out your >>>> box of random parts. For a testbench, you are going to go for something >>>> between these extremes.
How long is a piece of string? By keeping the interconnecting cables short, 4" or so, and a 5 foot cable from the PC, I don't expect problems with reflections. But it is prudent to allow for them anyway. The FTDI RS-422 cable seems to have a
not an issue. Since the interconnections between cards will be about five feet as well, it's unlikely to be an issue. The entire network will look like a lumped load, with the propagation time on the order of the rise/fall time. Even adding in a secondThere is no point in having a terminator at a driver (unless you are
talking about very high speed signals with serial resistors for slope
control). You will want to add a terminator at the far end of both
buses. This will give you a single terminator on the PC-to-slave bus,
which is fine as it is fixed direction, and two terminators on the
slave-to-PC bus, which is appropriate as it has no fixed direction.
It does if you are using it in a shared bus with multiple drivers. The line should still be organized as linear with minimal stubs and a terminator on each end. This is not my plan, so maybe I should stop discussing it.
Ideally, a bus should be (as you say) linear with minimal stubs and a terminator at each end - /except/ if one end is always driven. There is
no point in having a terminator at a driver. Think about it in terms of impedance - the driver is either driving a line high, or it is driving
it low. At any given time, one of the differential pair lines will have almost 0 ohm resistance to 0V, and the other will have nearly 0 ohm resistance to 5V. When the signal changes, these swap. Connecting a
100 ohm resistor across the lines at that point will make no difference whatsoever. The terminator is completely useless - it's just a waste of power. At the other end of the cable it's a different matter - there's
a cable full of resistance, capacitance and inductance between the terminator and the near 0 ohm driver, so the terminator resistor /does/
make a difference.
In more sophisticated tristate drivers, you would off (disconnect) the
local terminator whenever the driver is enabled. This is done in some multi-lane systems as it can significantly reduce power and make slope control and pulse shaping easier. (It's not something you'd be likely
to see on RS-485 buses.)
(I agree that your piece of string is of a size that should work fine
without reflections being a concern.)
Oddly enough, the RS-485 cable has a terminator that can be connected by the user, but that would be running through the cable separately from the transceiver signals, so essentially stubbed! I guess at 1 Mbps, 5 feet is less than the rise time, so
year. I may need to get with the factory and see if they can supply me directly.The speed of a signal in a copper cable is typically about 70% of the
They sell cables that have 5 m of cable, with a round trip of 30 ns or so. I think that would still not be significant in this application. The driver rise/fall times are 15 ns typ, 25 ns max.
speed of light, giving a minimum round-trip time closer to 45 ns than 30 >> ns. Not that it makes any difference here.
The problem I have now is finding parts to use for this. These devices seem to be in a catagory that are hit hard by the shortage. My product uses the SN65C1168EPW, which is very hard to find in quantity. My customer has mentioned 18,000 units next
Unfortunately, sourcing components these days is a much harder problem
than designing the systems.
On Saturday, November 5, 2022 at 2:57:30 PM UTC-4, David Brown wrote:controlled by FTDI software.
On 05/11/2022 18:23, Rick C wrote:
On Saturday, November 5, 2022 at 7:47:59 AM UTC-4, David Brown wrote:
The USB device is /not/ a processor - it is a converter between USB and
UART. And it is the USB device that controls the transmit enable signal
to the RS-485/RS-422 driver. There is no software on any processor
handling the transmit enable signal - the driver is enabled precisely
when the USB to UART device is sending data on the UART.
Actually, the FTDI device is a processor. I expect it actually has no UART, rather the entire thing is done in software. I recall there being code to download for various purposes, such as JTAG, but I forget the details. I'm pretty sure the TxEn is
As I mentioned earlier, this thread is getting seriously mixed-up. The
transmit enable discussion started with /RS-485/ - long before you
decided to use a hybrid bus and a RS-422 cable. You were concerned
about how the PC controlled the transmitter enable for the RS-485
driver, and I have been trying to explain how this works when you use a
decent UART device. You only confuse yourself when you jump to
discussing RS-422 here, in this bit of the conversation.
Ok, I'll stop talking about what I am doing.
error handling protocol than I will with bit errors on the bus. So I choose the most reliable solution, no error handling. So without an error handling protocol in the software, I don't need to do anything further to deal with errors.All communications have failures. Accept that as a principle, and
understand how to deal with it. It's not hard to do - it is certainly
much easier than trying to imagine and eliminate any possible cause of
trouble.
That's not a premise I have to deal with. I will also die. I'm not factoring that into the project either.
I don't need to eliminate "any possible cause of trouble". I only have to reach an effective level of reliability. As I've said, error handling protocols are complex and subject to failure. It's much more likely I will have more trouble with the
On 05/11/2022 21:42, Rick C wrote:controlled by FTDI software.
On Saturday, November 5, 2022 at 2:57:30 PM UTC-4, David Brown wrote:
On 05/11/2022 18:23, Rick C wrote:
On Saturday, November 5, 2022 at 7:47:59 AM UTC-4, David Brown wrote:
The USB device is /not/ a processor - it is a converter between USB and >> UART. And it is the USB device that controls the transmit enable signal >> to the RS-485/RS-422 driver. There is no software on any processor
handling the transmit enable signal - the driver is enabled precisely
when the USB to UART device is sending data on the UART.
Actually, the FTDI device is a processor. I expect it actually has no UART, rather the entire thing is done in software. I recall there being code to download for various purposes, such as JTAG, but I forget the details. I'm pretty sure the TxEn is
No, I think you are mixing things up. FTDI make a fair number of
devices, including some that /are/ processors or contain processors.
(That would their display controller devices, their USB host
controllers, amongst others.)
The code for using chips like the FT232H as a JTAG interface runs on the host PC, not FTDI chip - it is a DLL or so file (or OpenOCD, or other software). The chip has /hardware/ support for a few different serial interfaces - SPI, I²C, JTAG and UART.
error handling protocol than I will with bit errors on the bus. So I choose the most reliable solution, no error handling. So without an error handling protocol in the software, I don't need to do anything further to deal with errors.As I mentioned earlier, this thread is getting seriously mixed-up. The
transmit enable discussion started with /RS-485/ - long before you
decided to use a hybrid bus and a RS-422 cable. You were concerned
about how the PC controlled the transmitter enable for the RS-485
driver, and I have been trying to explain how this works when you use a >> decent UART device. You only confuse yourself when you jump to
discussing RS-422 here, in this bit of the conversation.
Ok, I'll stop talking about what I am doing.
We don't need to stop talking about it - we (everyone) just need to be a
bit clearer about the context. It's been fun to talk about, and its
great that you have a solution you are happy with, but it's a shame if
topic mixup leads to frustration.
All communications have failures. Accept that as a principle, and
understand how to deal with it. It's not hard to do - it is certainly
much easier than trying to imagine and eliminate any possible cause of
trouble.
That's not a premise I have to deal with. I will also die. I'm not factoring that into the project either.
I don't need to eliminate "any possible cause of trouble". I only have to reach an effective level of reliability. As I've said, error handling protocols are complex and subject to failure. It's much more likely I will have more trouble with the
I agree that error handling procedures can be difficult - and very
often, they are poorly tested and have their own bugs (hardware or software). Over-engineering can reduce overall reliability, rather than increase it. (A few years back, we had a project that had to be updated
to SIL safety certification requirements. Most of the changes reduced
the overall safety and reliability in order to fulfil the documentation
and certification requirements.)
For serial protocols, ensuring a brief pause between telegrams is
extremely simple and makes recovery possible after many kinds of errors. That's why it is found in virtually every serial protocol in wide use.
And like it or not, you have it already in your hybrid bus solution.
On Sunday, November 6, 2022 at 5:55:22 AM UTC-5, David Brown wrote:controlled by FTDI software.
On 05/11/2022 21:42, Rick C wrote:
On Saturday, November 5, 2022 at 2:57:30 PM UTC-4, David Brown wrote:
On 05/11/2022 18:23, Rick C wrote:
On Saturday, November 5, 2022 at 7:47:59 AM UTC-4, David Brown wrote:
The USB device is /not/ a processor - it is a converter between USB and >>>> UART. And it is the USB device that controls the transmit enable signal >>>> to the RS-485/RS-422 driver. There is no software on any processor
handling the transmit enable signal - the driver is enabled precisely
when the USB to UART device is sending data on the UART.
Actually, the FTDI device is a processor. I expect it actually has no UART, rather the entire thing is done in software. I recall there being code to download for various purposes, such as JTAG, but I forget the details. I'm pretty sure the TxEn is
No, I think you are mixing things up. FTDI make a fair number of
devices, including some that /are/ processors or contain processors.
(That would their display controller devices, their USB host
controllers, amongst others.)
The code for using chips like the FT232H as a JTAG interface runs on the
host PC, not FTDI chip - it is a DLL or so file (or OpenOCD, or other
software). The chip has /hardware/ support for a few different serial
interfaces - SPI, I²C, JTAG and UART.
They need code for the PC to run, but there is no reason to think they don't use a processor in the USB dongle.
error handling protocol than I will with bit errors on the bus. So I choose the most reliable solution, no error handling. So without an error handling protocol in the software, I don't need to do anything further to deal with errors.We don't need to stop talking about it - we (everyone) just need to be aAs I mentioned earlier, this thread is getting seriously mixed-up. The >>>> transmit enable discussion started with /RS-485/ - long before you
decided to use a hybrid bus and a RS-422 cable. You were concerned
about how the PC controlled the transmitter enable for the RS-485
driver, and I have been trying to explain how this works when you use a >>>> decent UART device. You only confuse yourself when you jump to
discussing RS-422 here, in this bit of the conversation.
Ok, I'll stop talking about what I am doing.
bit clearer about the context. It's been fun to talk about, and its
great that you have a solution you are happy with, but it's a shame if
topic mixup leads to frustration.
All communications have failures. Accept that as a principle, and
understand how to deal with it. It's not hard to do - it is certainly
much easier than trying to imagine and eliminate any possible cause of >>>> trouble.
That's not a premise I have to deal with. I will also die. I'm not factoring that into the project either.
I don't need to eliminate "any possible cause of trouble". I only have to reach an effective level of reliability. As I've said, error handling protocols are complex and subject to failure. It's much more likely I will have more trouble with the
that point the user will exit the software on the PC and start over. That gives a nice long delay for resyncing.I agree that error handling procedures can be difficult - and very
often, they are poorly tested and have their own bugs (hardware or
software). Over-engineering can reduce overall reliability, rather than
increase it. (A few years back, we had a project that had to be updated
to SIL safety certification requirements. Most of the changes reduced
the overall safety and reliability in order to fulfil the documentation
and certification requirements.)
For serial protocols, ensuring a brief pause between telegrams is
extremely simple and makes recovery possible after many kinds of errors.
That's why it is found in virtually every serial protocol in wide use.
And like it or not, you have it already in your hybrid bus solution.
There's no point to inter-message delays. If there is an error that causes a loss of framing, the devices will see that and ignore the message. As I've said, the real issue is that the message will not be responded to, and the software will fail. At
There's no point to inter-message delays. If there is an error that causes a loss of framing, the devices will see that and ignore the message. As I've said, the real issue is that the message will not be responded to, and the software will fail. Atthat point the user will exit the software on the PC and start over. That gives a nice long delay for resyncing.
And such handshaking is needed if you have need to handle noise in
packets.
Richard Damon <[email protected]> writes:
And such handshaking is needed if you have need to handle noise in
packets.
Once you acknowledge that noise and errors are even possible, some kind
of checksums or FEC seem appropriate in addition to a retry protocol.
On 06/11/2022 14:56, Rick C wrote:controlled by FTDI software.
On Sunday, November 6, 2022 at 5:55:22 AM UTC-5, David Brown wrote:
On 05/11/2022 21:42, Rick C wrote:
On Saturday, November 5, 2022 at 2:57:30 PM UTC-4, David Brown wrote: >>>> On 05/11/2022 18:23, Rick C wrote:
On Saturday, November 5, 2022 at 7:47:59 AM UTC-4, David Brown wrote: >>The USB device is /not/ a processor - it is a converter between USB and >>>> UART. And it is the USB device that controls the transmit enable signal >>>> to the RS-485/RS-422 driver. There is no software on any processor
handling the transmit enable signal - the driver is enabled precisely >>>> when the USB to UART device is sending data on the UART.
Actually, the FTDI device is a processor. I expect it actually has no UART, rather the entire thing is done in software. I recall there being code to download for various purposes, such as JTAG, but I forget the details. I'm pretty sure the TxEn is
No, I think you are mixing things up. FTDI make a fair number of
devices, including some that /are/ processors or contain processors.
(That would their display controller devices, their USB host
controllers, amongst others.)
The code for using chips like the FT232H as a JTAG interface runs on the >> host PC, not FTDI chip - it is a DLL or so file (or OpenOCD, or other
software). The chip has /hardware/ support for a few different serial
interfaces - SPI, I²C, JTAG and UART.
They need code for the PC to run, but there is no reason to think they don't use a processor in the USB dongle.
There is no reason to think that they /do/ have a processor there. I
should imagine you would have no problem making the programmable logic needed for controlling a UART/SPI/I²C/JTAG/GPIO port, and USB slave
devices are rarely made in software (even on the XMOS they prefer
hardware blocks for USB). Why would anyone use a /processor/ for some
simple digital hardware? I am not privy to the details of the FTDI
design beyond their published documents, but it seems pretty clear to me that there is no processor in sight.
One thing I'm a bit confused about, is the wiring of the EIA/TIA 568B or 568A cables. Both standards are used, but as far as I can tell, the only difference is the colors! The green and orange twisted pairs are reversed on both ends, making thecables electrically identical, other than the colors used for a given pair. The only difference is, the different pairs have different twist pitch, to help reduce crosstalk. But the numbers are not specified in the spec, so I don't see how this could
Why would the color be an issue, to the point of creating two different specs???
Obviously I'm missing something. I will need to check a cable before I design the boards, lol.
On Saturday, November 5, 2022 at 6:58:24 AM UTC-4, David Brown wrote:
In UART communication, this is handled at the protocol level rather than
the hardware (though some UART hardware may have "idle detect" signals
when more than 11 bits of high level are seen in a row). Some
UART-based protocols also use a "break" signal between frames - that is
a string of at least 11 bits of low level.
If you do not have such pauses, and a receiver is out of step,
You have failed to explain how a receiver would get "out of step". The receiver syncs to every character transmitted. If all characters are received, what else do you need? How does it get "out of step"?
On 11/6/22 8:56 AM, Rick C wrote:that point the user will exit the software on the PC and start over. That gives a nice long delay for resyncing.
There's no point to inter-message delays. If there is an error that causes a loss of framing, the devices will see that and ignore the message. As I've said, the real issue is that the message will not be responded to, and the software will fail. At
If the only way to handle a missed message is to abort the whole
software system, that seems to be a pretty bad system.
Note, if the master sends out a message, and waits for a response, with
a retry if the message is not replied to, that naturally puts a pause in
the communication bus for inter-message synchronization.
Based on your description, I can't imagine the master starting a message
for another slave until after the first one answers, or you will
interfere with the arbitration control of the reply bus.
In a dedicated link, after the link is established, it might be possible that one side just starts streaming data continously to the other side,
but most protocals will have some sort of at least occational
handshaking back, so a loss of sync can stop the flow to re-establish
the syncronization. And such handshaking is needed if you have need to handle noise in packets.
On 11/6/22 6:37 PM, Paul Rubin wrote:
Richard Damon <[email protected]> writes:
And such handshaking is needed if you have need to handle noise in
packets.
Once you acknowledge that noise and errors are even possible, some kindYes, the messages should have some form of checksum in them to identify
of checksums or FEC seem appropriate in addition to a retry protocol.
bad packets. That should be part of the message definition.
On Sunday, November 6, 2022 at 3:54:04 PM UTC-5, David Brown wrote:is controlled by FTDI software.
On 06/11/2022 14:56, Rick C wrote:
On Sunday, November 6, 2022 at 5:55:22 AM UTC-5, David Brown wrote:
On 05/11/2022 21:42, Rick C wrote:
On Saturday, November 5, 2022 at 2:57:30 PM UTC-4, David Brown wrote:
On 05/11/2022 18:23, Rick C wrote:
On Saturday, November 5, 2022 at 7:47:59 AM UTC-4, David Brown wrote: >> >>The USB device is /not/ a processor - it is a converter between USB and >> >>>> UART. And it is the USB device that controls the transmit enable signal >> >>>> to the RS-485/RS-422 driver. There is no software on any processor
handling the transmit enable signal - the driver is enabled precisely >> >>>> when the USB to UART device is sending data on the UART.
Actually, the FTDI device is a processor. I expect it actually has no UART, rather the entire thing is done in software. I recall there being code to download for various purposes, such as JTAG, but I forget the details. I'm pretty sure the TxEn
these interfaces. The small processor can actually be a very small amount of chip area. Typical MCUs are dominated by the memory blocks. With a small memory an MCU could easily be smaller than dedicated logic. Even many of the I/O blocks, like UARTs,There is no reason to think that they /do/ have a processor there. INo, I think you are mixing things up. FTDI make a fair number of
devices, including some that /are/ processors or contain processors.
(That would their display controller devices, their USB host
controllers, amongst others.)
The code for using chips like the FT232H as a JTAG interface runs on the >> >> host PC, not FTDI chip - it is a DLL or so file (or OpenOCD, or other
software). The chip has /hardware/ support for a few different serial
interfaces - SPI, I²C, JTAG and UART.
They need code for the PC to run, but there is no reason to think they don't use a processor in the USB dongle.
should imagine you would have no problem making the programmable logic
needed for controlling a UART/SPI/I²C/JTAG/GPIO port, and USB slave
devices are rarely made in software (even on the XMOS they prefer
hardware blocks for USB). Why would anyone use a /processor/ for some
simple digital hardware? I am not privy to the details of the FTDI
design beyond their published documents, but it seems pretty clear to me
that there is no processor in sight.
I don't agree. These interfaces are not so simple when you consider the level of flexibility in implementing many different interfaces in one part. XMOS is nothing like this. A small processor running at high speed would easily implement any of
On 2022-11-07 Rick C wrote in comp.arch.embedded:is controlled by FTDI software.
On Sunday, November 6, 2022 at 3:54:04 PM UTC-5, David Brown wrote:
On 06/11/2022 14:56, Rick C wrote:
On Sunday, November 6, 2022 at 5:55:22 AM UTC-5, David Brown wrote:
On 05/11/2022 21:42, Rick C wrote:
On Saturday, November 5, 2022 at 2:57:30 PM UTC-4, David Brown wrote: >> >>>> On 05/11/2022 18:23, Rick C wrote:
On Saturday, November 5, 2022 at 7:47:59 AM UTC-4, David Brown wrote:
The USB device is /not/ a processor - it is a converter between USB and
UART. And it is the USB device that controls the transmit enable signal
to the RS-485/RS-422 driver. There is no software on any processor >> >>>> handling the transmit enable signal - the driver is enabled precisely
when the USB to UART device is sending data on the UART.
Actually, the FTDI device is a processor. I expect it actually has no UART, rather the entire thing is done in software. I recall there being code to download for various purposes, such as JTAG, but I forget the details. I'm pretty sure the TxEn
interfaces. The small processor can actually be a very small amount of chip area. Typical MCUs are dominated by the memory blocks. With a small memory an MCU could easily be smaller than dedicated logic. Even many of the I/O blocks, like UARTs, can beThere is no reason to think that they /do/ have a processor there. INo, I think you are mixing things up. FTDI make a fair number of
devices, including some that /are/ processors or contain processors. >> >> (That would their display controller devices, their USB host
controllers, amongst others.)
The code for using chips like the FT232H as a JTAG interface runs on the
host PC, not FTDI chip - it is a DLL or so file (or OpenOCD, or other >> >> software). The chip has /hardware/ support for a few different serial >> >> interfaces - SPI, I²C, JTAG and UART.
They need code for the PC to run, but there is no reason to think they don't use a processor in the USB dongle.
should imagine you would have no problem making the programmable logic
needed for controlling a UART/SPI/I²C/JTAG/GPIO port, and USB slave
devices are rarely made in software (even on the XMOS they prefer
hardware blocks for USB). Why would anyone use a /processor/ for some
simple digital hardware? I am not privy to the details of the FTDI
design beyond their published documents, but it seems pretty clear to me >> that there is no processor in sight.
I don't agree. These interfaces are not so simple when you consider the level of flexibility in implementing many different interfaces in one part. XMOS is nothing like this. A small processor running at high speed would easily implement any of these
Why are you discussing this? Out of academic curiosity? Then please continue. But what does it matter for your system implementation? There
is just a UART/SPI/I²C/JTAG/GPIO peripheral and your software won't care how this peripheral is implemented, as long as it behaves as expected.
On Monday, November 7, 2022 at 5:26:06 AM UTC-5, Stef wrote:TxEn is controlled by FTDI software.
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Sunday, November 6, 2022 at 3:54:04 PM UTC-5, David Brown wrote:
On 06/11/2022 14:56, Rick C wrote:
On Sunday, November 6, 2022 at 5:55:22 AM UTC-5, David Brown wrote:
On 05/11/2022 21:42, Rick C wrote:
On Saturday, November 5, 2022 at 2:57:30 PM UTC-4, David Brown wrote: >> >> >>>> On 05/11/2022 18:23, Rick C wrote:
On Saturday, November 5, 2022 at 7:47:59 AM UTC-4, David Brown wrote:
The USB device is /not/ a processor - it is a converter between USB and
UART. And it is the USB device that controls the transmit enable signal
to the RS-485/RS-422 driver. There is no software on any processor >> >> >>>> handling the transmit enable signal - the driver is enabled precisely
when the USB to UART device is sending data on the UART.
Actually, the FTDI device is a processor. I expect it actually has no UART, rather the entire thing is done in software. I recall there being code to download for various purposes, such as JTAG, but I forget the details. I'm pretty sure the
these interfaces. The small processor can actually be a very small amount of chip area. Typical MCUs are dominated by the memory blocks. With a small memory an MCU could easily be smaller than dedicated logic. Even many of the I/O blocks, like UARTs, canThere is no reason to think that they /do/ have a processor there. INo, I think you are mixing things up. FTDI make a fair number of
devices, including some that /are/ processors or contain processors. >> >> >> (That would their display controller devices, their USB host
controllers, amongst others.)
The code for using chips like the FT232H as a JTAG interface runs on the
host PC, not FTDI chip - it is a DLL or so file (or OpenOCD, or other >> >> >> software). The chip has /hardware/ support for a few different serial >> >> >> interfaces - SPI, I²C, JTAG and UART.
They need code for the PC to run, but there is no reason to think they don't use a processor in the USB dongle.
should imagine you would have no problem making the programmable logic
needed for controlling a UART/SPI/I²C/JTAG/GPIO port, and USB slave
devices are rarely made in software (even on the XMOS they prefer
hardware blocks for USB). Why would anyone use a /processor/ for some
simple digital hardware? I am not privy to the details of the FTDI
design beyond their published documents, but it seems pretty clear to me >> >> that there is no processor in sight.
I don't agree. These interfaces are not so simple when you consider the level of flexibility in implementing many different interfaces in one part. XMOS is nothing like this. A small processor running at high speed would easily implement any of
Why are you discussing this? Out of academic curiosity? Then please
continue. But what does it matter for your system implementation? There
is just a UART/SPI/I²C/JTAG/GPIO peripheral and your software won't care
how this peripheral is implemented, as long as it behaves as expected.
I care. Don't you?
I remember when I came to the realization of why an MCU was so cost effective compared to programmable or even dedicated logic. It's because the MCU program is a FSM, using the instructions stored in the memory. These instruction are essentiallylogic, which is connected through the CPU logic, creating a very low cost solution to a wide variety of problems, because of the very low cost of memory compared to dedicated or programmable logic.
On Sunday, November 6, 2022 at 6:34:59 PM UTC-5, Richard Damon wrote:that point the user will exit the software on the PC and start over. That gives a nice long delay for resyncing.
On 11/6/22 8:56 AM, Rick C wrote:
There's no point to inter-message delays. If there is an error that causes a loss of framing, the devices will see that and ignore the message. As I've said, the real issue is that the message will not be responded to, and the software will fail. At
If the only way to handle a missed message is to abort the whole
software system, that seems to be a pretty bad system.
You would certainly think that if your error rate was more than once a hundred years. I expect to be long dead before an RS-422 bus only 10 feet long burps a bit error.
Note, if the master sends out a message, and waits for a response, with
a retry if the message is not replied to, that naturally puts a pause in
the communication bus for inter-message synchronization.
The pause is already there by virtue of the protocol. Commands and replies are on different busses.
Based on your description, I can't imagine the master starting a message
for another slave until after the first one answers, or you will
interfere with the arbitration control of the reply bus.
Exactly! Now you are starting to catch on.
value.In a dedicated link, after the link is established, it might be possible
that one side just starts streaming data continously to the other side,
Except that there is no data to stream. Maybe you haven't been around for the full conversation. The protocol is command/reply for reading and writing registers and selecting which unit the registers are being accessed. The "stream" is an 8 bit
but most protocals will have some sort of at least occational
handshaking back, so a loss of sync can stop the flow to re-establish
the syncronization. And such handshaking is needed if you have need to
handle noise in packets.
??? Every command has a reply. How is that not a handshake???
On 2022-11-05 Rick C wrote in comp.arch.embedded:
On Saturday, November 5, 2022 at 6:58:24 AM UTC-4, David Brown wrote:
In UART communication, this is handled at the protocol level rather than >>> the hardware (though some UART hardware may have "idle detect" signals
when more than 11 bits of high level are seen in a row). Some
UART-based protocols also use a "break" signal between frames - that is
a string of at least 11 bits of low level.
If you do not have such pauses, and a receiver is out of step,
You have failed to explain how a receiver would get "out of step". The receiver syncs to every character transmitted. If all characters are received, what else do you need? How does it get "out of step"?
I have seen this happen in long messages (few kB) with no pauses between characters and transmitter and receiver set to 8,N,1. It seemed that the receiver needed the complete stop bit and then immediately saw the low
of the next start bit. Detecting the edge when it was ready to see it,
not when it actually happened. When the receiver is slightly slower than
the transmitter, this caused the detection of the start bit (and
therefor the whole character) to shift a tiny bit. This added up over
the character stream until it eventually failed.
Lowering the baud rate did not solve the issue, but inserting pauses
after a number of chars did. What also solved it was setting the
transmitter to 2 stop bits and the receiver to one stop bit. This was a
one way stream and this may not be possible on a bi-directional stream.
I would expect a sensible UART implementation to allow for a slightly
shorter stop bit to compensate for issues like this. But apparently this
UART did not do so in the 1 stop bit setting. I have not tested if
setting both ends to 2 stop bits also solved the problem.
In more sophisticated tristate drivers, you would off (disconnect) the
local terminator whenever the driver is enabled. This is done in some multi-lane systems as it can significantly reduce power and make slope control and pulse shaping easier. (It's not something you'd be likely
to see on RS-485 buses.)
On 2022-11-05 Rick C wrote in comp.arch.embedded:
On Saturday, November 5, 2022 at 6:58:24 AM UTC-4, David Brown wrote:
In UART communication, this is handled at the protocol level rather than >> the hardware (though some UART hardware may have "idle detect" signals
when more than 11 bits of high level are seen in a row). Some
UART-based protocols also use a "break" signal between frames - that is >> a string of at least 11 bits of low level.
If you do not have such pauses, and a receiver is out of step,
You have failed to explain how a receiver would get "out of step". The receiver syncs to every character transmitted. If all characters are received, what else do you need? How does it get "out of step"?I have seen this happen in long messages (few kB) with no pauses between characters and transmitter and receiver set to 8,N,1. It seemed that the receiver needed the complete stop bit and then immediately saw the low
of the next start bit. Detecting the edge when it was ready to see it,
not when it actually happened. When the receiver is slightly slower than
the transmitter, this caused the detection of the start bit (and
therefor the whole character) to shift a tiny bit. This added up over
the character stream until it eventually failed.
Lowering the baud rate did not solve the issue, but inserting pauses
after a number of chars did. What also solved it was setting the
transmitter to 2 stop bits and the receiver to one stop bit. This was a
one way stream and this may not be possible on a bi-directional stream.
I would expect a sensible UART implementation to allow for a slightly shorter stop bit to compensate for issues like this. But apparently this UART did not do so in the 1 stop bit setting. I have not tested if
setting both ends to 2 stop bits also solved the problem.
On 2022-11-07 Rick C wrote in comp.arch.embedded:At that point the user will exit the software on the PC and start over. That gives a nice long delay for resyncing.
On Sunday, November 6, 2022 at 6:34:59 PM UTC-5, Richard Damon wrote:
On 11/6/22 8:56 AM, Rick C wrote:
There's no point to inter-message delays. If there is an error that causes a loss of framing, the devices will see that and ignore the message. As I've said, the real issue is that the message will not be responded to, and the software will fail.
If the only way to handle a missed message is to abort the whole
software system, that seems to be a pretty bad system.
You would certainly think that if your error rate was more than once a hundred years. I expect to be long dead before an RS-422 bus only 10 feet long burps a bit error.I would not dare to implement a serial protocol without any form of
error checking, on any length of cable.
You mention ESD somewhere. This can be a serious disturbance that can
easily corrupt a few bits.
Reminds me of a product where we got windows blue screens during ESD
testing on a device connected via an FTDI USB to serial adapter. Cable length less than 6 feet.
Note, if the master sends out a message, and waits for a response, with >> a retry if the message is not replied to, that naturally puts a pause in >> the communication bus for inter-message synchronization.
The pause is already there by virtue of the protocol. Commands and replies are on different busses.
Based on your description, I can't imagine the master starting a message >> for another slave until after the first one answers, or you will
interfere with the arbitration control of the reply bus.
Exactly! Now you are starting to catch on.So you do wait for a reply, and a reply is only expected on a valid
message? What if there is no reply, do you retry? If so, you already have implemented some basic error checking. For more robustness you could (I would) add some kind of CRC.
On Monday, November 7, 2022 at 7:07:43 AM UTC-4, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 5:26:06 AM UTC-5, Stef wrote:No, I don't. We do use FTDI chips in our designs to interface a serial
On 2022-11-07 Rick C wrote in comp.arch.embedded:
I care. Don't you?
port to USB. And we also use ready made FTDI cables. We use these chips
and cables based on their specifications in datasheets and user guides
etc. I have never felt the need to invesitigate how the UART/USB
functionality was actually implemented inside the chip. What would I do
with this knowledge? In a design I must rely on the behaviour as
specified in the datasheet.
It's hard to imagine an engineer with no curiosity.
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 5:26:06 AM UTC-5, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
I care. Don't you?No, I don't. We do use FTDI chips in our designs to interface a serial
port to USB. And we also use ready made FTDI cables. We use these chips
and cables based on their specifications in datasheets and user guides
etc. I have never felt the need to invesitigate how the UART/USB functionality was actually implemented inside the chip. What would I do
with this knowledge? In a design I must rely on the behaviour as
specified in the datasheet.
logic, which is connected through the CPU logic, creating a very low cost solution to a wide variety of problems, because of the very low cost of memory compared to dedicated or programmable logic.I remember when I came to the realization of why an MCU was so cost effective compared to programmable or even dedicated logic. It's because the MCU program is a FSM, using the instructions stored in the memory. These instruction are essentially
This is what I would call 'academic interest', and that is perfectly
fine. And this knowledge might help you think differently about solving
a problem in your own design. But it will make no difference in how you
will imlement this chip (or cable) in your design.
On Monday, November 7, 2022 at 6:55:27 AM UTC-4, Stef wrote:At that point the user will exit the software on the PC and start over. That gives a nice long delay for resyncing.
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Sunday, November 6, 2022 at 6:34:59 PM UTC-5, Richard Damon wrote:
On 11/6/22 8:56 AM, Rick C wrote:
There's no point to inter-message delays. If there is an error that causes a loss of framing, the devices will see that and ignore the message. As I've said, the real issue is that the message will not be responded to, and the software will fail.
I would not dare to implement a serial protocol without any form ofIf the only way to handle a missed message is to abort the whole
software system, that seems to be a pretty bad system.
You would certainly think that if your error rate was more than once a hundred years. I expect to be long dead before an RS-422 bus only 10 feet long burps a bit error.
error checking, on any length of cable.
You mention ESD somewhere. This can be a serious disturbance that can
easily corrupt a few bits.
Yes, I mentioned ESD somewhere. This is testing newly constructed circuit boards, so is used in an ESD controlled environment.
Reminds me of a product where we got windows blue screens during ESD
testing on a device connected via an FTDI USB to serial adapter. Cable
length less than 6 feet.
I assume you mean some other device was being ESD tested? This is not being used in an ESD testing lab. Was the FTDI serial cable RS-232 by any chance? Being single ended, that is much less tolerant of noise.
error control. The format has one character to indicate the "command" type. If that character is corrupted, the command is not used, unless it is changed to another valid character (3 of 256 chance).So you do wait for a reply, and a reply is only expected on a validNote, if the master sends out a message, and waits for a response, with >> >> a retry if the message is not replied to, that naturally puts a pause in >> >> the communication bus for inter-message synchronization.
The pause is already there by virtue of the protocol. Commands and replies are on different busses.
Based on your description, I can't imagine the master starting a message >> >> for another slave until after the first one answers, or you will
interfere with the arbitration control of the reply bus.
Exactly! Now you are starting to catch on.
message? What if there is no reply, do you retry? If so, you already have
implemented some basic error checking. For more robustness you could (I
would) add some kind of CRC.
There should not be any messages other than "valid" messages. I don't recall specifically what the slave does on messages with bit errors, but I'm pretty sure it simply doesn't know they have bit errors. The message has no checksum or other bit
Again, there's no reason to "detect" errors since I've implemented no error protocol. That is many times more complex than simply ignoring the errors, which works because errors don't happen often enough to have an impact on testing.
On the Apollo moon missions, they took no precautions against damage from micrometeoroids, because the effort required was not commensurate with the likelihood of the event.
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 7:07:43 AM UTC-4, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 5:26:06 AM UTC-5, Stef wrote:No, I don't. We do use FTDI chips in our designs to interface a serial
On 2022-11-07 Rick C wrote in comp.arch.embedded:
I care. Don't you?
port to USB. And we also use ready made FTDI cables. We use these chips >> and cables based on their specifications in datasheets and user guides
etc. I have never felt the need to invesitigate how the UART/USB
functionality was actually implemented inside the chip. What would I do >> with this knowledge? In a design I must rely on the behaviour as
specified in the datasheet.
It's hard to imagine an engineer with no curiosity.Yes, that's hard. But imagining an engineer who does not care about the internal structure of every single chip he uses is a lot easier (for
me). I tend to focus my curiiosity on things that matter to me, don't
you?
On 2022-11-07 Rick C wrote in comp.arch.embedded:fail. At that point the user will exit the software on the PC and start over. That gives a nice long delay for resyncing.
On Monday, November 7, 2022 at 6:55:27 AM UTC-4, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Sunday, November 6, 2022 at 6:34:59 PM UTC-5, Richard Damon wrote: >> >> On 11/6/22 8:56 AM, Rick C wrote:
There's no point to inter-message delays. If there is an error that causes a loss of framing, the devices will see that and ignore the message. As I've said, the real issue is that the message will not be responded to, and the software will
I would not dare to implement a serial protocol without any form ofIf the only way to handle a missed message is to abort the whole
software system, that seems to be a pretty bad system.
You would certainly think that if your error rate was more than once a hundred years. I expect to be long dead before an RS-422 bus only 10 feet long burps a bit error.
error checking, on any length of cable.
You mention ESD somewhere. This can be a serious disturbance that can
easily corrupt a few bits.
Yes, I mentioned ESD somewhere. This is testing newly constructed circuit boards, so is used in an ESD controlled environment.
You wrote:
"I could probably get away with TTL level signals, but I'd like to have
the ESD protection these RS-422 chips give. That additional noise
immunity means there is an extremely small chance of bit errors. If we
have problems, the error handling can be added."
This led me to believe you were expecting actual ESD discharges that
could disturb your messages.
ESD protection is just that: protection against device damage
I do not believe ESD protection does anything to improve noise immunity.
It just increases the ESD level at which the device will be damaged.
And if you have an ESD controlled environment, that is not actually
needed.
Reminds me of a product where we got windows blue screens during ESD
testing on a device connected via an FTDI USB to serial adapter. Cable
length less than 6 feet.
I assume you mean some other device was being ESD tested? This is not being used in an ESD testing lab. Was the FTDI serial cable RS-232 by any chance? Being single ended, that is much less tolerant of noise.No a device with an FTDI chip on it was tested. USB cable was <= 6 feet
and serial ports were only a few centimeters of TTL level PCB traces.
This was reproducable with an evaluation kit with only USB connected.
control. The format has one character to indicate the "command" type. If that character is corrupted, the command is not used, unless it is changed to another valid character (3 of 256 chance).So you do wait for a reply, and a reply is only expected on a validNote, if the master sends out a message, and waits for a response, with
a retry if the message is not replied to, that naturally puts a pause in
the communication bus for inter-message synchronization.
The pause is already there by virtue of the protocol. Commands and replies are on different busses.
Based on your description, I can't imagine the master starting a message
for another slave until after the first one answers, or you will
interfere with the arbitration control of the reply bus.
Exactly! Now you are starting to catch on.
message? What if there is no reply, do you retry? If so, you already have >> implemented some basic error checking. For more robustness you could (I >> would) add some kind of CRC.
There should not be any messages other than "valid" messages. I don't recall specifically what the slave does on messages with bit errors, but I'm pretty sure it simply doesn't know they have bit errors. The message has no checksum or other bit error
Okay, the slaves are already implemented? Missed that.
So there is some very basic error detection: the command must be valid.
And if it is not and the slave does not reply, what does the master do?
Again, there's no reason to "detect" errors since I've implemented no error protocol. That is many times more complex than simply ignoring the errors, which works because errors don't happen often enough to have an impact on testing.A test rig that ignores errors. I don't know the requirements of this
test and how bad it would be to have an invalid pass/fail result.
On the Apollo moon missions, they took no precautions against damage from micrometeoroids, because the effort required was not commensurate with the likelihood of the event.I am not sure what they could have done, but adding effective shields
would probably have prohibitive weight consequences, if at all possible.
But if you can believe the movie Apollo 13, thre is a real danger from micrometeorites.
On Monday, November 7, 2022 at 1:20:33 PM UTC-4, Stef wrote:fail. At that point the user will exit the software on the PC and start over. That gives a nice long delay for resyncing.
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 6:55:27 AM UTC-4, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Sunday, November 6, 2022 at 6:34:59 PM UTC-5, Richard Damon wrote: >> >> >> On 11/6/22 8:56 AM, Rick C wrote:
There's no point to inter-message delays. If there is an error that causes a loss of framing, the devices will see that and ignore the message. As I've said, the real issue is that the message will not be responded to, and the software will
You wrote:I would not dare to implement a serial protocol without any form ofIf the only way to handle a missed message is to abort the whole
software system, that seems to be a pretty bad system.
You would certainly think that if your error rate was more than once a hundred years. I expect to be long dead before an RS-422 bus only 10 feet long burps a bit error.
error checking, on any length of cable.
You mention ESD somewhere. This can be a serious disturbance that can
easily corrupt a few bits.
Yes, I mentioned ESD somewhere. This is testing newly constructed circuit boards, so is used in an ESD controlled environment.
"I could probably get away with TTL level signals, but I'd like to have
the ESD protection these RS-422 chips give. That additional noise
immunity means there is an extremely small chance of bit errors. If we
have problems, the error handling can be added."
This led me to believe you were expecting actual ESD discharges that
could disturb your messages.
ESD protection is just that: protection against device damage
I do not believe ESD protection does anything to improve noise immunity.
It just increases the ESD level at which the device will be damaged.
Yes, you are right. My language there is poor. I should have said I prefer the noise immunity the RS-422 devices have compared to TTL devices *in addition to* the ESD immunity.
And if you have an ESD controlled environment, that is not actually
needed.
In theory, but I can't control how these will be used in the future. ESD immunity is something I want designed into any application that is connected by a cable.
you say, ESD protection is about damage, not operation.No a device with an FTDI chip on it was tested. USB cable was <= 6 feetReminds me of a product where we got windows blue screens during ESD
testing on a device connected via an FTDI USB to serial adapter. Cable
length less than 6 feet.
I assume you mean some other device was being ESD tested? This is not being used in an ESD testing lab. Was the FTDI serial cable RS-232 by any chance? Being single ended, that is much less tolerant of noise.
and serial ports were only a few centimeters of TTL level PCB traces.
This was reproducable with an evaluation kit with only USB connected.
So you were shooting high voltages into a device and were surprised the PC it was connected to crashed? I'm not following this at all. I'm pretty sure the FTDI cable is not rated to provide isolation. That has nothing to do with ESD protection. As
error control. The format has one character to indicate the "command" type. If that character is corrupted, the command is not used, unless it is changed to another valid character (3 of 256 chance).So you do wait for a reply, and a reply is only expected on a validNote, if the master sends out a message, and waits for a response, with
a retry if the message is not replied to, that naturally puts a pause in
the communication bus for inter-message synchronization.
The pause is already there by virtue of the protocol. Commands and replies are on different busses.
Based on your description, I can't imagine the master starting a message
for another slave until after the first one answers, or you will
interfere with the arbitration control of the reply bus.
Exactly! Now you are starting to catch on.
message? What if there is no reply, do you retry? If so, you already have >> >> implemented some basic error checking. For more robustness you could (I >> >> would) add some kind of CRC.
There should not be any messages other than "valid" messages. I don't recall specifically what the slave does on messages with bit errors, but I'm pretty sure it simply doesn't know they have bit errors. The message has no checksum or other bit
Okay, the slaves are already implemented? Missed that.
A test fixture is in use, with software on the PC. There's no reason to change the protocol in the new test fixture and software unless there is a need, a new requirement.
PITA. The only character that is required for sure, is the "X", which at the moment can be one of three from the possible characters (don't recall if they are 8 bit or 7). I also don't recall if parity checking is used.So there is some very basic error detection: the command must be valid.
And if it is not and the slave does not reply, what does the master do?
The command being valid is based on as single character. The command is something like, "01 23 X<cr><lf>". I suppose the CR LF might also be required, but I don't recall. It might require one and ignore the other. The whole CR LF thing is such a
I do know that I had a flaw in the initial setup that gave intermittent errors. I had the hardest time finding the problem because of using bias in where to look. I tried adding re-transmission, which helped, but it borked up the code pretty well. Iguess my software skills are not so good. In the end, it was an Ariane problem where the UART in the FPGA was existing code that was reused. Thinking it was a previously validated module, it was not suspected... at all. Eventually I realized it did
Since that was solved, we've tested thousands of UUTs with no interface bit errors. So I have no worries about this.
decaying. Well, maybe a bit more likely.Again, there's no reason to "detect" errors since I've implemented no error protocol. That is many times more complex than simply ignoring the errors, which works because errors don't happen often enough to have an impact on testing.A test rig that ignores errors. I don't know the requirements of this
test and how bad it would be to have an invalid pass/fail result.
Since the test will be run, over night, every few seconds, with all UUT errors logged, the chances of the same bit error happening the same way, causing the same miss of a UUT failure some thousands of time (about 7,000), is on the order as a proton
may be ERRORS!"On the Apollo moon missions, they took no precautions against damage from micrometeoroids, because the effort required was not commensurate with the likelihood of the event.I am not sure what they could have done, but adding effective shields
would probably have prohibitive weight consequences, if at all possible.
But if you can believe the movie Apollo 13, thre is a real danger from
micrometeorites.
Real, even if very small danger. That's the point. In this case, the impact is small, the likelihood is small, and the work to mitigate the problem is far more effort than justifiable, no matter how emotional people may get about "Errors! OMG, there
Maybe I need a heavy duty cabinet to protect against the very real possibility of meteors?
https://abc7chicago.com/meteor-california-destroys-home-shower/12425011/
On Monday, November 7, 2022 at 12:57:27 PM UTC-4, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 7:07:43 AM UTC-4, Stef wrote:Yes, that's hard. But imagining an engineer who does not care about the
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 5:26:06 AM UTC-5, Stef wrote:No, I don't. We do use FTDI chips in our designs to interface a serial
On 2022-11-07 Rick C wrote in comp.arch.embedded:
I care. Don't you?
port to USB. And we also use ready made FTDI cables. We use these chips >> >> and cables based on their specifications in datasheets and user guides
etc. I have never felt the need to invesitigate how the UART/USB
functionality was actually implemented inside the chip. What would I do >> >> with this knowledge? In a design I must rely on the behaviour as
specified in the datasheet.
It's hard to imagine an engineer with no curiosity.
internal structure of every single chip he uses is a lot easier (for
me). I tend to focus my curiiosity on things that matter to me, don't
you?
By definition curiosity is, "an eager desire to know or learn about something". That's not limited to things I *need* to know about. In fact, I don't limit my curiosity at all. It's a desire, not an act.
I could shove the details of tests into the FPGAs, so the commands are
more like, run test 1 on channel number 2. That would cut the number
of tests significantly, but require much more work in updating the
FPGA software.
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 12:57:27 PM UTC-4, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 7:07:43 AM UTC-4, Stef wrote:Yes, that's hard. But imagining an engineer who does not care about the
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 5:26:06 AM UTC-5, Stef wrote:No, I don't. We do use FTDI chips in our designs to interface a serial >> >> port to USB. And we also use ready made FTDI cables. We use these chips >> >> and cables based on their specifications in datasheets and user guides >> >> etc. I have never felt the need to invesitigate how the UART/USB
On 2022-11-07 Rick C wrote in comp.arch.embedded:
I care. Don't you?
functionality was actually implemented inside the chip. What would I do >> >> with this knowledge? In a design I must rely on the behaviour as
specified in the datasheet.
It's hard to imagine an engineer with no curiosity.
internal structure of every single chip he uses is a lot easier (for
me). I tend to focus my curiiosity on things that matter to me, don't
you?
By definition curiosity is, "an eager desire to know or learn about something". That's not limited to things I *need* to know about. In fact, I don't limit my curiosity at all. It's a desire, not an act.
Learn about something != learn about everything
Matter to me != *need* to know about
My not caring abbout the innards of a particular chip seems to let you
think I don't care about anything. But we are not discussing my
interests here, but your bus.
On 2022-11-07 Rick C wrote in comp.arch.embedded:fail. At that point the user will exit the software on the PC and start over. That gives a nice long delay for resyncing.
On Monday, November 7, 2022 at 1:20:33 PM UTC-4, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 6:55:27 AM UTC-4, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Sunday, November 6, 2022 at 6:34:59 PM UTC-5, Richard Damon wrote:
On 11/6/22 8:56 AM, Rick C wrote:
There's no point to inter-message delays. If there is an error that causes a loss of framing, the devices will see that and ignore the message. As I've said, the real issue is that the message will not be responded to, and the software will
You wrote:I would not dare to implement a serial protocol without any form ofIf the only way to handle a missed message is to abort the whole
software system, that seems to be a pretty bad system.
You would certainly think that if your error rate was more than once a hundred years. I expect to be long dead before an RS-422 bus only 10 feet long burps a bit error.
error checking, on any length of cable.
You mention ESD somewhere. This can be a serious disturbance that can >> >> easily corrupt a few bits.
Yes, I mentioned ESD somewhere. This is testing newly constructed circuit boards, so is used in an ESD controlled environment.
"I could probably get away with TTL level signals, but I'd like to have >> the ESD protection these RS-422 chips give. That additional noise
immunity means there is an extremely small chance of bit errors. If we
have problems, the error handling can be added."
This led me to believe you were expecting actual ESD discharges that
could disturb your messages.
ESD protection is just that: protection against device damage
I do not believe ESD protection does anything to improve noise immunity. >> It just increases the ESD level at which the device will be damaged.
Yes, you are right. My language there is poor. I should have said I prefer the noise immunity the RS-422 devices have compared to TTL devices *in addition to* the ESD immunity.
you say, ESD protection is about damage, not operation.And if you have an ESD controlled environment, that is not actually
needed.
In theory, but I can't control how these will be used in the future. ESD immunity is something I want designed into any application that is connected by a cable.
Yes, alway protect accessible parts.
No a device with an FTDI chip on it was tested. USB cable was <= 6 feet >> and serial ports were only a few centimeters of TTL level PCB traces.Reminds me of a product where we got windows blue screens during ESD >> >> testing on a device connected via an FTDI USB to serial adapter. Cable >> >> length less than 6 feet.
I assume you mean some other device was being ESD tested? This is not being used in an ESD testing lab. Was the FTDI serial cable RS-232 by any chance? Being single ended, that is much less tolerant of noise.
This was reproducable with an evaluation kit with only USB connected.
So you were shooting high voltages into a device and were surprised the PC it was connected to crashed? I'm not following this at all. I'm pretty sure the FTDI cable is not rated to provide isolation. That has nothing to do with ESD protection. As
Ofcourse not into a device. But all over the enclosure, as is required
to pass EMC testing. These discharges cause current spikes that can
induce currents in parts of your circuits. Part of ESD testing also uses coupling planes, where you fire on a metal plate 'near' the device. That
can also give a lot of noise. All these things may not cause device
damage like direct ESD discharges, but they can disturb the device operation. Depending on the expected performance level, this may cause a fail. For medical devices you usually cannot get away with worse than "temporary loss of function and recovery without operator intervention".
ESD protection is indeed about damage prevention. But passing an ESD
test usually requires more than just preventing damage.
How would you rate a phone that resets every time you pick it up when
you have not properly discharged yourself from static electricity? It
may just reboot and work fine after that, but it would still be a crappy phone.
error control. The format has one character to indicate the "command" type. If that character is corrupted, the command is not used, unless it is changed to another valid character (3 of 256 chance).So you do wait for a reply, and a reply is only expected on a validNote, if the master sends out a message, and waits for a response, with
a retry if the message is not replied to, that naturally puts a pause in
the communication bus for inter-message synchronization.
The pause is already there by virtue of the protocol. Commands and replies are on different busses.
Based on your description, I can't imagine the master starting a message
for another slave until after the first one answers, or you will
interfere with the arbitration control of the reply bus.
Exactly! Now you are starting to catch on.
message? What if there is no reply, do you retry? If so, you already have
implemented some basic error checking. For more robustness you could (I
would) add some kind of CRC.
There should not be any messages other than "valid" messages. I don't recall specifically what the slave does on messages with bit errors, but I'm pretty sure it simply doesn't know they have bit errors. The message has no checksum or other bit
Okay, the slaves are already implemented? Missed that.
A test fixture is in use, with software on the PC. There's no reason to change the protocol in the new test fixture and software unless there is a need, a new requirement.Ah, existing stuff.
The only character that is required for sure, is the "X", which at the moment can be one of three from the possible characters (don't recall if they are 8 bit or 7). I also don't recall if parity checking is used.So there is some very basic error detection: the command must be valid. >> And if it is not and the slave does not reply, what does the master do?
The command being valid is based on as single character. The command is something like, "01 23 X<cr><lf>". I suppose the CR LF might also be required, but I don't recall. It might require one and ignore the other. The whole CR LF thing is such a PITA.
Okay, more restrictions on valid messages, yet more error detection
present already. ;-) No real detection since there's no awareness of the error. It's like saying your transmission has "error detection" because it can stop working because a gear tooth broke off and jammed the whole transmission breaking more gears.
guess my software skills are not so good. In the end, it was an Ariane problem where the UART in the FPGA was existing code that was reused. Thinking it was a previously validated module, it was not suspected... at all. Eventually I realized it did notI do know that I had a flaw in the initial setup that gave intermittent errors. I had the hardest time finding the problem because of using bias in where to look. I tried adding re-transmission, which helped, but it borked up the code pretty well. I
Since that was solved, we've tested thousands of UUTs with no interface bit errors. So I have no worries about this.
decaying. Well, maybe a bit more likely.Again, there's no reason to "detect" errors since I've implemented no error protocol. That is many times more complex than simply ignoring the errors, which works because errors don't happen often enough to have an impact on testing.A test rig that ignores errors. I don't know the requirements of this
test and how bad it would be to have an invalid pass/fail result.
Since the test will be run, over night, every few seconds, with all UUT errors logged, the chances of the same bit error happening the same way, causing the same miss of a UUT failure some thousands of time (about 7,000), is on the order as a proton
Another layer of error detection. ;-)
On Monday, November 7, 2022 at 4:30:37 PM UTC-4, Stef wrote:...
My not caring abbout the innards of a particular chip seems to let you
think I don't care about anything. But we are not discussing my
interests here, but your bus.
Seems to me you wanted to talk about my interests when you said, "Why are you discussing this?" and then continued discussing that issue for some half dozen more posts.
On Monday, November 7, 2022 at 6:00:09 AM UTC-4, Stef wrote:is the middle of the bit) and then immediately start looking for the leading edge of the next start bit. The receiver will then be synchronized to the new character bit timing and it will never slip. That gives up to ±5% combined timing error
On 2022-11-05 Rick C wrote in comp.arch.embedded:
On Saturday, November 5, 2022 at 6:58:24 AM UTC-4, David Brown wrote:I have seen this happen in long messages (few kB) with no pauses between
In UART communication, this is handled at the protocol level rather than >>>> the hardware (though some UART hardware may have "idle detect" signals >>>> when more than 11 bits of high level are seen in a row). Some
UART-based protocols also use a "break" signal between frames - that is >>>> a string of at least 11 bits of low level.
If you do not have such pauses, and a receiver is out of step,
You have failed to explain how a receiver would get "out of step". The receiver syncs to every character transmitted. If all characters are received, what else do you need? How does it get "out of step"?
characters and transmitter and receiver set to 8,N,1. It seemed that the
receiver needed the complete stop bit and then immediately saw the low
of the next start bit. Detecting the edge when it was ready to see it,
not when it actually happened. When the receiver is slightly slower than
the transmitter, this caused the detection of the start bit (and
therefor the whole character) to shift a tiny bit. This added up over
the character stream until it eventually failed.
Lowering the baud rate did not solve the issue, but inserting pauses
after a number of chars did. What also solved it was setting the
transmitter to 2 stop bits and the receiver to one stop bit. This was a
one way stream and this may not be possible on a bi-directional stream.
I would expect a sensible UART implementation to allow for a slightly
shorter stop bit to compensate for issues like this. But apparently this
UART did not do so in the 1 stop bit setting. I have not tested if
setting both ends to 2 stop bits also solved the problem.
If a UART receiver can not properly receive a message like this, it is defective. The point of the start and stop bits are to provide the synchronization. The receiver simply needs to detect the stop be state (by sampling where the receiver thinks
If the receiver waits until a later time, such as the expected end of the received stop bit, to start looking for a start bit leading edge, it will not be able to tolerate a timing error where the transmitter is faster than the receiver making thetiming tolerance unipolar, i.e. 5% rather than ±5%.
That's a receiver design flaw, or the transmitter is sending short stop bits, which you can easily see on the scope with a delayed trigger control.
You should be able to diagnose which end has the problem by connecting a different type of receiver to the stream. If a different receiver UART is able to receive the messages without fault, the problem is obviously the failing receiver.
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 4:30:37 PM UTC-4, Stef wrote:...
My not caring abbout the innards of a particular chip seems to let you
think I don't care about anything. But we are not discussing my
interests here, but your bus.
Seems to me you wanted to talk about my interests when you said, "Why are you discussing this?" and then continued discussing that issue for some half dozen more posts.That was not my intention. It seemed to me that you cared about the
internal implementation of the FTDI chip in relation to your bus
problem. I just wanted to point out that is of no concern for your bus operation. And then I just got dragged in. ;-)
Rick C <[email protected]> writes:
I could shove the details of tests into the FPGAs, so the commands are more like, run test 1 on channel number 2. That would cut the number
of tests significantly, but require much more work in updating the
FPGA software.
Are we circling back to the idea putting a microprocessor on the test
board? Ivan Sutherland famously called this a wheel of reincarnation:
http://www.cap-lore.com/Hardware/Wheel.html
On 11/7/22 11:05 AM, Rick C wrote:the middle of the bit) and then immediately start looking for the leading edge of the next start bit. The receiver will then be synchronized to the new character bit timing and it will never slip. That gives up to ±5% combined timing error tolerance.
On Monday, November 7, 2022 at 6:00:09 AM UTC-4, Stef wrote:
On 2022-11-05 Rick C wrote in comp.arch.embedded:
On Saturday, November 5, 2022 at 6:58:24 AM UTC-4, David Brown wrote: >>>I have seen this happen in long messages (few kB) with no pauses between >> characters and transmitter and receiver set to 8,N,1. It seemed that the >> receiver needed the complete stop bit and then immediately saw the low
In UART communication, this is handled at the protocol level rather than
the hardware (though some UART hardware may have "idle detect" signals >>>> when more than 11 bits of high level are seen in a row). Some
UART-based protocols also use a "break" signal between frames - that is >>>> a string of at least 11 bits of low level.
If you do not have such pauses, and a receiver is out of step,
You have failed to explain how a receiver would get "out of step". The receiver syncs to every character transmitted. If all characters are received, what else do you need? How does it get "out of step"?
of the next start bit. Detecting the edge when it was ready to see it,
not when it actually happened. When the receiver is slightly slower than >> the transmitter, this caused the detection of the start bit (and
therefor the whole character) to shift a tiny bit. This added up over
the character stream until it eventually failed.
Lowering the baud rate did not solve the issue, but inserting pauses
after a number of chars did. What also solved it was setting the
transmitter to 2 stop bits and the receiver to one stop bit. This was a >> one way stream and this may not be possible on a bi-directional stream. >>
I would expect a sensible UART implementation to allow for a slightly
shorter stop bit to compensate for issues like this. But apparently this >> UART did not do so in the 1 stop bit setting. I have not tested if
setting both ends to 2 stop bits also solved the problem.
If a UART receiver can not properly receive a message like this, it is defective. The point of the start and stop bits are to provide the synchronization. The receiver simply needs to detect the stop be state (by sampling where the receiver thinks is
timing tolerance unipolar, i.e. 5% rather than ±5%.If the receiver waits until a later time, such as the expected end of the received stop bit, to start looking for a start bit leading edge, it will not be able to tolerate a timing error where the transmitter is faster than the receiver making the
That's a receiver design flaw, or the transmitter is sending short stop bits, which you can easily see on the scope with a delayed trigger control.
You should be able to diagnose which end has the problem by connecting a different type of receiver to the stream. If a different receiver UART is able to receive the messages without fault, the problem is obviously the failing receiver.
YOU may consider it a design flaw, but I have seen too many serial ports having this flaw in them to just totally ignore it.
Yes, the "robust" design will allow for a short stop bit, but you can't count on all serial adaptors allowing for it.
Part of the problem is that (at least as far as I know) the Asynchronous Serial Format isn't actually a "Published Standard", but just an
de-facto protocol that is simple enough that it mostly just works, but
still hides a few gotchas for corner cases.
On Monday, November 7, 2022 at 7:07:50 PM UTC-4, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 4:30:37 PM UTC-4, Stef wrote:...
That was not my intention. It seemed to me that you cared aboutMy not caring abbout the innards of a particular chip seems to
let you think I don't care about anything. But we are not
discussing my interests here, but your bus.
Seems to me you wanted to talk about my interests when you said,
"Why are you discussing this?" and then continued discussing that
issue for some half dozen more posts.
the internal implementation of the FTDI chip in relation to your
bus problem. I just wanted to point out that is of no concern for
your bus operation. And then I just got dragged in. ;-)
I'm always curious about how things are implemented. I thought I had
heard somewhere that the FTDI chip was a fast, but small processor.
I design those for use in FPGA designs and they can be very
effective. Often the code is very minimal.
On Monday, November 7, 2022 at 8:02:19 PM UTC-4, Richard Damon wrote:the middle of the bit) and then immediately start looking for the leading edge of the next start bit. The receiver will then be synchronized to the new character bit timing and it will never slip. That gives up to ±5% combined timing error tolerance.
On 11/7/22 11:05 AM, Rick C wrote:
On Monday, November 7, 2022 at 6:00:09 AM UTC-4, Stef wrote:
On 2022-11-05 Rick C wrote in comp.arch.embedded:
On Saturday, November 5, 2022 at 6:58:24 AM UTC-4, David Brown wrote: >>>>>I have seen this happen in long messages (few kB) with no pauses between >>>> characters and transmitter and receiver set to 8,N,1. It seemed that the >>>> receiver needed the complete stop bit and then immediately saw the low >>>> of the next start bit. Detecting the edge when it was ready to see it, >>>> not when it actually happened. When the receiver is slightly slower than >>>> the transmitter, this caused the detection of the start bit (and
In UART communication, this is handled at the protocol level rather than >>>>>> the hardware (though some UART hardware may have "idle detect" signals >>>>>> when more than 11 bits of high level are seen in a row). Some
UART-based protocols also use a "break" signal between frames - that is >>>>>> a string of at least 11 bits of low level.
If you do not have such pauses, and a receiver is out of step,
You have failed to explain how a receiver would get "out of step". The receiver syncs to every character transmitted. If all characters are received, what else do you need? How does it get "out of step"?
therefor the whole character) to shift a tiny bit. This added up over
the character stream until it eventually failed.
Lowering the baud rate did not solve the issue, but inserting pauses
after a number of chars did. What also solved it was setting the
transmitter to 2 stop bits and the receiver to one stop bit. This was a >>>> one way stream and this may not be possible on a bi-directional stream. >>>>
I would expect a sensible UART implementation to allow for a slightly
shorter stop bit to compensate for issues like this. But apparently this >>>> UART did not do so in the 1 stop bit setting. I have not tested if
setting both ends to 2 stop bits also solved the problem.
If a UART receiver can not properly receive a message like this, it is defective. The point of the start and stop bits are to provide the synchronization. The receiver simply needs to detect the stop be state (by sampling where the receiver thinks is
timing tolerance unipolar, i.e. 5% rather than ±5%.
If the receiver waits until a later time, such as the expected end of the received stop bit, to start looking for a start bit leading edge, it will not be able to tolerate a timing error where the transmitter is faster than the receiver making the
bits (ignoring timing accuracy). So it thinks it is in the middle of the stop bit when the bit timing is complete. It would need to have more hardware to time to the end of the stop bit. This might be present, for other purposes, but it should not beYOU may consider it a design flaw, but I have seen too many serial ports
That's a receiver design flaw, or the transmitter is sending short stop bits, which you can easily see on the scope with a delayed trigger control.
You should be able to diagnose which end has the problem by connecting a different type of receiver to the stream. If a different receiver UART is able to receive the messages without fault, the problem is obviously the failing receiver.
having this flaw in them to just totally ignore it.
That is exceedingly hard to imagine, since it would take extra logic to implement. The logic of a UART is to first, detect the start bit which lands the state machine in the middle of said start bit which then times to the middle of all subsequent
I guess I'm not certain that would cause an error, actually. It would initiate the start bit detection logic, and as long as it does not require seeing the idle condition before detecting the start bit condition, it would still work. Again, this isexpected by the definition of asynchronous format. This would result in a grosser offset in timing the middle of the bits, so the allowable timing error is less. But it will still work otherwise. 5% is a very large combined error. Most devices are
Yes, the "robust" design will allow for a short stop bit, but you can't
count on all serial adaptors allowing for it.
There's always garbage designs. I'm surprised I never ran into one. I guess being crystal controlled, there was never enough error to add up to a bit.
tried to ask questions since and even if they seem like stupid questions, I don't read the specs wrong.Part of the problem is that (at least as far as I know) the Asynchronous
Serial Format isn't actually a "Published Standard", but just an
de-facto protocol that is simple enough that it mostly just works, but
still hides a few gotchas for corner cases.
True, but anyone designing chips should understand what they are designing. If they don't, you get garbage. I learned that lesson in a class in school where I screwed up a detail on a program I wrote, because I didn't understand the spec. I've always
On Monday, November 7, 2022 at 7:07:50 PM UTC-4, Stef wrote:
On 2022-11-07 Rick C wrote in comp.arch.embedded:
On Monday, November 7, 2022 at 4:30:37 PM UTC-4, Stef wrote:...
That was not my intention. It seemed to me that you cared about theMy not caring abbout the innards of a particular chip seems to let you >>>> think I don't care about anything. But we are not discussing my
interests here, but your bus.
Seems to me you wanted to talk about my interests when you said, "Why are you discussing this?" and then continued discussing that issue for some half dozen more posts.
internal implementation of the FTDI chip in relation to your bus
problem. I just wanted to point out that is of no concern for your bus
operation. And then I just got dragged in. ;-)
I'm always curious about how things are implemented. I thought I had heard somewhere that the FTDI chip was a fast, but small processor. I design those for use in FPGA designs and they can be very effective. Often the code is very minimal.
On 11/7/22 8:15 PM, Rick C wrote:bits (ignoring timing accuracy). So it thinks it is in the middle of the stop bit when the bit timing is complete. It would need to have more hardware to time to the end of the stop bit. This might be present, for other purposes, but it should not be
On Monday, November 7, 2022 at 8:02:19 PM UTC-4, Richard Damon wrote:
YOU may consider it a design flaw, but I have seen too many serial ports >> having this flaw in them to just totally ignore it.
That is exceedingly hard to imagine, since it would take extra logic to implement. The logic of a UART is to first, detect the start bit which lands the state machine in the middle of said start bit which then times to the middle of all subsequent
Depends on how you design it. IF you start a counter at the leading edge
of the start bit and then detect the counter at its middle value, then
the stop bit ends when the counter finally expires at the END of the
stop bit.
expected by the definition of asynchronous format. This would result in a grosser offset in timing the middle of the bits, so the allowable timing error is less. But it will still work otherwise. 5% is a very large combined error. Most devices are timedI guess I'm not certain that would cause an error, actually. It would initiate the start bit detection logic, and as long as it does not require seeing the idle condition before detecting the start bit condition, it would still work. Again, this is
IF you don't start the looking for the start bit until the time has
passed for the END of the stop bit, and the receiver is 0.1% slow, then every bit you lose 0.1% of a bit, or 1% per character, so after 50 consecutive characters you are 1/2 a bit late, and getting errors.
Yes, the "robust" design will allow for a short stop bit, but you can't >> count on all serial adaptors allowing for it.
There's always garbage designs. I'm surprised I never ran into one. I guess being crystal controlled, there was never enough error to add up to a bit.As I pointed out, 0.1% means 50 characters. 0.001% means 5000
characters, long enough string of characters and eventually you hit the problem.
If you only use short messages, you never have a problem.
tried to ask questions since and even if they seem like stupid questions, I don't read the specs wrong.Part of the problem is that (at least as far as I know) the Asynchronous >> Serial Format isn't actually a "Published Standard", but just an
de-facto protocol that is simple enough that it mostly just works, but
still hides a few gotchas for corner cases.
True, but anyone designing chips should understand what they are designing. If they don't, you get garbage. I learned that lesson in a class in school where I screwed up a detail on a program I wrote, because I didn't understand the spec. I've always
The problem is that if you describe the sampling as "Middle of bit",
then going to the end of the stop bit makes sense.
If you are adding functionality like RS-485 control that needs to know
when that end of bit is, and it is easy to forget that the receiver has different needs than the transmitter.
On Tuesday, November 8, 2022 at 7:54:59 AM UTC-4, Richard Damon wrote:flaw would be such a PITA and expose the flaw, that the part would become a pariah.
IF you don't start the looking for the start bit until the time has
passed for the END of the stop bit, and the receiver is 0.1% slow, then
every bit you lose 0.1% of a bit, or 1% per character, so after 50
consecutive characters you are 1/2 a bit late, and getting errors.
There you go! You have just proven that no one would design a UART to work this way and for it to be used in the market place. There would be too many applications where the data burst would cause it to not work. Programming around such a design
On 9/11/22 00:50, Rick C wrote:would be such a PITA and expose the flaw, that the part would become a pariah.
On Tuesday, November 8, 2022 at 7:54:59 AM UTC-4, Richard Damon wrote:
IF you don't start the looking for the start bit until the time has
passed for the END of the stop bit, and the receiver is 0.1% slow, then >> every bit you lose 0.1% of a bit, or 1% per character, so after 50
consecutive characters you are 1/2 a bit late, and getting errors.
There you go! You have just proven that no one would design a UART to work this way and for it to be used in the market place. There would be too many applications where the data burst would cause it to not work. Programming around such a design flaw
Yeah, but you can still insist that the stop bit fills 99%, or 90% of
the required time, and not get that pathology.
On Tuesday, November 8, 2022 at 7:45:14 PM UTC-4, Clifford Heath wrote:would be such a PITA and expose the flaw, that the part would become a pariah. >> Yeah, but you can still insist that the stop bit fills 99%, or 90% of
On 9/11/22 00:50, Rick C wrote:
On Tuesday, November 8, 2022 at 7:54:59 AM UTC-4, Richard Damon wrote:
IF you don't start the looking for the start bit until the time has
passed for the END of the stop bit, and the receiver is 0.1% slow, then >>>> every bit you lose 0.1% of a bit, or 1% per character, so after 50
consecutive characters you are 1/2 a bit late, and getting errors.
There you go! You have just proven that no one would design a UART to work this way and for it to be used in the market place. There would be too many applications where the data burst would cause it to not work. Programming around such a design flaw
aren't offset in one direction. Looking for the start bit in the middle of the stop bit gives a total of 5% tolerance, pretty much taking mistiming out of the list of problems for async data transmission. Drop that to 0.05% (your 99% example) and youthe required time, and not get that pathology.
I'm not clear on what you are saying. The larger the clock difference, the earlier the receiver has to look for the start bit. It will work just fine with the start bit check being delayed until the end of the stop bit, as long as the timing clocks
On 9/11/22 11:46, Rick C wrote:flaw would be such a PITA and expose the flaw, that the part would become a pariah.
On Tuesday, November 8, 2022 at 7:45:14 PM UTC-4, Clifford Heath wrote:
On 9/11/22 00:50, Rick C wrote:
On Tuesday, November 8, 2022 at 7:54:59 AM UTC-4, Richard Damon wrote: >>>> IF you don't start the looking for the start bit until the time has >>>> passed for the END of the stop bit, and the receiver is 0.1% slow, then >>>> every bit you lose 0.1% of a bit, or 1% per character, so after 50
consecutive characters you are 1/2 a bit late, and getting errors.
There you go! You have just proven that no one would design a UART to work this way and for it to be used in the market place. There would be too many applications where the data burst would cause it to not work. Programming around such a design
aren't offset in one direction. Looking for the start bit in the middle of the stop bit gives a total of 5% tolerance, pretty much taking mistiming out of the list of problems for async data transmission. Drop that to 0.05% (your 99% example) and you areYeah, but you can still insist that the stop bit fills 99%, or 90% of
the required time, and not get that pathology.
I'm not clear on what you are saying. The larger the clock difference, the earlier the receiver has to look for the start bit. It will work just fine with the start bit check being delayed until the end of the stop bit, as long as the timing clocks
Go back to the first words I quoted from Richard:
"
IF you don't start the looking for the start bit until the time has
passed for the END of the stop bit, and the receiver is 0.1% slow, then every bit you lose 0.1% of a bit
"
But if you wait until 95% of the stop bit time, and allow a new start
bit to come early by 5%, then it doesn't matter if "the receiver is 0.1% slow" and you don't lose sync; the 5% early doesn't mount up over "50 consecutive characters".
Same if you wait 99% and the new start bit is only 1% early.
So your "There you go! You have just proven..." was a bogus situation proposed by Richard, that's trivially avoided, and basically all actual UARTs will do that,
On Tuesday, November 8, 2022 at 7:54:59 AM UTC-4, Richard Damon wrote:bits (ignoring timing accuracy). So it thinks it is in the middle of the stop bit when the bit timing is complete. It would need to have more hardware to time to the end of the stop bit. This might be present, for other purposes, but it should not be
On 11/7/22 8:15 PM, Rick C wrote:
On Monday, November 7, 2022 at 8:02:19 PM UTC-4, Richard Damon wrote:
YOU may consider it a design flaw, but I have seen too many serial ports >>>> having this flaw in them to just totally ignore it.
That is exceedingly hard to imagine, since it would take extra logic to implement. The logic of a UART is to first, detect the start bit which lands the state machine in the middle of said start bit which then times to the middle of all subsequent
logic to distinguish the end of a bit.Depends on how you design it. IF you start a counter at the leading edge
of the start bit and then detect the counter at its middle value, then
the stop bit ends when the counter finally expires at the END of the
stop bit.
There is still some extra logic to distinguish the condition. There is a bit timing counter, and a counter to track which bit you are in. Everything happening in the operation of the UART is happening at the middle of a bit. Then you need extra
expected by the definition of asynchronous format. This would result in a grosser offset in timing the middle of the bits, so the allowable timing error is less. But it will still work otherwise. 5% is a very large combined error. Most devices are timedI guess I'm not certain that would cause an error, actually. It would initiate the start bit detection logic, and as long as it does not require seeing the idle condition before detecting the start bit condition, it would still work. Again, this is
flaw would be such a PITA and expose the flaw, that the part would become a pariah.IF you don't start the looking for the start bit until the time has
passed for the END of the stop bit, and the receiver is 0.1% slow, then
every bit you lose 0.1% of a bit, or 1% per character, so after 50
consecutive characters you are 1/2 a bit late, and getting errors.
There you go! You have just proven that no one would design a UART to work this way and for it to be used in the market place. There would be too many applications where the data burst would cause it to not work. Programming around such a design
I recall the Intel USART was such a part for other technical flaws. So they finally came out with a new version that fixed the problems.
On 11/8/22 8:50 AM, Rick C wrote:bits (ignoring timing accuracy). So it thinks it is in the middle of the stop bit when the bit timing is complete. It would need to have more hardware to time to the end of the stop bit. This might be present, for other purposes, but it should not be
On Tuesday, November 8, 2022 at 7:54:59 AM UTC-4, Richard Damon wrote:
On 11/7/22 8:15 PM, Rick C wrote:
On Monday, November 7, 2022 at 8:02:19 PM UTC-4, Richard Damon wrote: >>>> YOU may consider it a design flaw, but I have seen too many serial ports
having this flaw in them to just totally ignore it.
That is exceedingly hard to imagine, since it would take extra logic to implement. The logic of a UART is to first, detect the start bit which lands the state machine in the middle of said start bit which then times to the middle of all subsequent
to distinguish the end of a bit.Depends on how you design it. IF you start a counter at the leading edge >> of the start bit and then detect the counter at its middle value, then
the stop bit ends when the counter finally expires at the END of the
stop bit.
There is still some extra logic to distinguish the condition. There is a bit timing counter, and a counter to track which bit you are in. Everything happening in the operation of the UART is happening at the middle of a bit. Then you need extra logic
Nope, simplest logic is to have your 8x sub-bit counter start at 0 and
count up starting on the leading edge, on the count values of 3, 4, and
5 you sample the bit for noise detection, and roll over from 7 to 0 for
the next bit, and count to the next bit. You stop the counter when it
rolls from 7 to 0 in the stop bit, and counts past the stop bit.
expected by the definition of asynchronous format. This would result in a grosser offset in timing the middle of the bits, so the allowable timing error is less. But it will still work otherwise. 5% is a very large combined error. Most devices are timedI guess I'm not certain that would cause an error, actually. It would initiate the start bit detection logic, and as long as it does not require seeing the idle condition before detecting the start bit condition, it would still work. Again, this is
would be such a PITA and expose the flaw, that the part would become a pariah.IF you don't start the looking for the start bit until the time has
passed for the END of the stop bit, and the receiver is 0.1% slow, then >> every bit you lose 0.1% of a bit, or 1% per character, so after 50
consecutive characters you are 1/2 a bit late, and getting errors.
There you go! You have just proven that no one would design a UART to work this way and for it to be used in the market place. There would be too many applications where the data burst would cause it to not work. Programming around such a design flaw
Except that we have bought many USB serial ports with just this flaw in them.
So I guess the nobody actually exists.
Seem to be based on an FTDI chip, but maybe just a "look alike", where
they did bare minimum design work.
The key point is that very few applications actually do have very long uninterrupted sequences of characters, and typical PCs will tend to naturally add small spaces just becuase the OS isn't that great. Doesn't require much to fix the issue.
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